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參數(shù)資料
| 型號： | AD9739A-FMC-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL W/FMC CONN FPGA DEV |
| 設計資源： | AD9739A-FMC-EBZ Gerber Files AD9739A-FMC-EBZ Layout |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5G |
| 數(shù)據(jù)接口： | 串行，SPI? |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9739A |
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Data Sheet
AD9737A/AD9739A
Rev. | Page 45 of 64
DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE
Table 19. Data Receiver Controller_Data Sample Delay Value Register (LVDS_REC_CNT2 and LVDS_REC_CNT3)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x11
SMP_DEL[1:0]
[7:6]
R/W
0x11
Controller enabled: the 10-bit value (with a maximum of 384) represents
the start value for the delay line used by the state machine to sample data.
Leave at the default setting of 167, which is near the midpoint of the delay line.
Controller disabled: the value sets the actual value of the delay line.
0x12
SMP_DEL[9:2]
[7:0]
R/W
0x25
DATA RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION
Table 20. Data Receiver Controller_DCI Delay Value (LVDS_REC_CNT4)/Window and Phase Rotation Register (LVDS_REC_CNT5)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x13
DCI_DEL[3:0]
[7:4]
R/W
0x0111
Refer to the DCI_DEL description in Register 0x14.
FINE_DEL_
SKW[3:0]
[3:0]
R/W
0x0001
A 4-bit value sets the difference (that is, window) for the DCI PRE and POST
sampling clocks. Leave at the default value of 1 for a narrow window.
0x14
DCI_DEL[9:4]
[5:0]
R/W
0x001010
Controller enabled: the 10-bit value (with a maximum of 384) represents
the start value for the delay line used by the state machine to sample the
DCI input. Leave at the default setting of 167, which is near the midpoint
of the delay line.
Controller disabled: the value sets the actual value of the delay line.
DATA RECEIVER CONTROLLER_DELAY LINE STATUS
Table 21. Data Receiver Controller_Delay Line Status Register (LVDS_REC_STAT[1:4])
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x19
SMP_DEL[1:0]
[7:6]
R
0x00
The actual value of the DCI and data delay lines are determined by the
data receiver controller (when enabled) after the state machine completes
its search and enters track mode. Note that these values should be equal.
0x1A
SMP_DEL[9:2]
[7:0]
R
0x00
0x1B
DCI_DEL[1:0]
[7:6]
R
0x00
0x1C
DCI_DEL[9:2]
[7:0]
R
0x00
DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS
Table 22. Data Receiver Controller Lock/Tracking Status Register (LVDS_REC_STAT9)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x21
RCVR_TRK_ON
3
R
0x0
0 = tracking not established, 1 = tracking established.
RCVR_FE_ON
2
R
0x0
0 = find edge state machine is not active, 1 = find edge state machine is
active.
RCVR_LST
1
R
0x0
0 = controller has not lost lock, 1 = controller has lost lock.
RCVR_LCK
0
R
0x0
0 = controller is not locked, 1 = controller is locked.
C
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