參數(shù)資料
型號(hào)： AD9737ABBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 49/64頁(yè)
文件大?。?/td> 0K
描述： IC DAC 11BIT 2.5GSPS RF 160BGA
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 13ns
位數(shù)： 11
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 960µW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 160-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 160-CSPBGA（12x12）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 1 電流，單極
采樣率（每秒）： 2.5G
Data Sheet
AD9737A/AD9739A
Rev. | Page 53 of 64
0
2
4
6
8
10
12
14
16
18
0
40
80
120
160
200
240
280
320
360
400
440
DELAY LINE TAP
MU
PH
A
S
E
NOM_P1
SLOW_P1
FAST_P1
09616-
05
0
Figure 167. Mu Phase Characteristics of Three Devices from Different Process
Lots at 1.2 GSPS
The Mu phase characteristics can vary significantly among devices
due to gm variations in the digital delay line that are sensitive to
process skews, along with temperature and supply. As a result,
careful selection of the target phase location is required such that
the Mu controller can converge upon this phase location for all
devices.
Figure 167 shows the Mu phase characteristics of three devices
at 25°C from slow, nominal, and fast skew lots at 1.2 GSPS. Note
that a 6 Mu phase setting does not map to any delay line tap
setting for the fast process skew case; therefore, another target Mu
phase is recommended at this clock rate.
Table 27 provides a list of recommended Mu phase/slope settings
over the specified clock range of the AD9737A/AD9739A based
on the considerations previously described. These values should
be used to ensure robust operation of the Mu controller.
Table 27. Recommended Target Mu Phase Settings vs. Clock Rate
Clock Rate (GSPS)
Slope
Mu Phase
0.8
6
0.9
4
1.0
+
5
1.1
+
8
1.2
+
12
1.3
12
1.4
10
1.5
8
1.6 to 2.5
6
After the Mu controller completes its search and establishes lock
on the target Mu phase, it attempts to maintain a constant timing
relationship between the two clock domains over the specified
temperature and supply range. If the Mu controller requests a Mu
delay setting that exceeds the tapped delay line range (that is, <0
or >432), the Mu controller can lose lock, causing possible system
disruption (that is, can generate an IRQ or restart the search). To
avoid this scenario, symmetrical guard bands are recommended at
each end of the Mu delay range. The guard band scaling is such
that one LSB of Guard[4:0] (Register 0x29) corresponds to eight
LSBs of MUDEL[8:0] (Register 0x28). The recommended guard
band setting of 11 (that is, Register 0x29 = 0xCB) corresponds
to 88 LSBs, thus providing sufficient margin.
Mu Controller Initialization Description
The Mu controller must be initialized and placed into track mode
as a first step in the SPI boot sequence. The following steps are
required for initialization of the Mu controller. Note that the
AD9737A/AD9739A data sheet specifications and characterization
data are based on the following Mu controller settings:
1. Turn on the phase detector with boost (Register 0x24 = 0x30).
2. Enable the Mu delay controller duty-cycle correction
circuitry and specify the recommended slope for phase.
(that is, Register 0x25 = 0x80 corresponds to a negative slope).
3. Specify search/track mode with a recommended target
phase, SET_PHS, of 6 (for example) and an initial
MUDEL[8:0] setting of 216 (Register 0x27 = 0x46 and
Register 0x28 = 0x6C).
4. Set search tolerance to exact, and retry if the search fails its
initial attempt. Also, set the guard band to the recommended
setting of 11 (Register 0x29 = 0xCB).
5. Set the Mu controller tracking gain to the recommended
setting and enable the Mu controller state machine
(Register 0x26 = 0x03).
On completion of the last step, the Mu controller begins a search
algorithm that starts with an initial delay setting specified by the
MUDEL bits (that is, 216, which corresponds to the midpoint of
the delay line). The initial search algorithm works by sweeping
through different Mu delay values in an alternating manner until
the desired phase (that is, a SET_PHS of 4) is exactly measured.
When the desired phase is measured, the slope of the phase
measurement is then calculated and compared against the
specified slope (slope = negative).
If everything matches, the search algorithm is finished. If not, the
search continues in both directions until an exact match is found
or a programmable guard band is reached in one of the directions.
When the guard band is reached, the search still continues but
only in the opposite direction. If the desired phase is not found
before the guard band is reached in the second direction, the search
changes back to the alternating mode and continues looking
within the guard band. The typical locking time for the Mu
controller is approximately 180 k DAC cycles (at 2 GSPS ~ 75 s).
The search fails if the Mu delay controller reaches the endpoints.
The Mu controller can be configured to retry (Register 0x29,
Bit 6) the search or stop. For applications that have a micro-
controller, the preferred approach is to poll the MU_LKD status
bit (Register 0x2A, Bit 0) after the typical locking time has expired.
This method lets the system controller check the status of other
system parameters (that is, power supplies and clock source)
before reattempting the search (by writing 0x03 to Register 0x26).
C
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