參數(shù)資料
型號： AD9736
廠商： Analog Devices, Inc.
英文描述： 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述： 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換
文件頁數(shù)： 6/42頁
文件大小： 934K
代理商： AD9736
AD9736/AD9735/AD9734
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
Pin No.
Rev. PrJ | Page 6 of 42
Name
Description
A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3
A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,
B10, B11, C4, C5, C6, C9, C10, C11, D4, D5,
D6, D9, D10, D11
A7, B7, C7, D7
A8, B8, C8, D8
A12, A13, B12, B13, C12, C13, D12, D13
A14, K1
VDDC
1.8V, Clock supply
VSSA
Analog supply ground
IOUTB
IOUTA
VDDA
DNC
DAC negative output, 10mA to 30mA full scale output current
DAC positive output, 10mA to 30mA full scale output current
3.3V Analog supply
Do Not Connect
Nominal 1.2V reference tied to analog ground via 10kohm resistor to generate a
120uA reference current
Bandgap voltage reference I/O, tie to analog ground via 1nF capacitor, output
impedance approximately 5kohms
Clock supply ground
Factory test, output current proportional to absolute temperature, approximately
10uA at 25C with approximately 20nA/C slope
Negative, Positive DAC clock input (DACCLK)
Analog supply ground shield
If PIN_MODE = 0, IRQ: Active low open-drain interrupt request output, pull up to
VDD3.3 with 10kohm resistor
If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = two’s complement input
data format, 1 = unsigned
If PIN_MODE = 0, RESET: 1 resets the AD9736
If PIN_MODE = 1, PD: 1 puts the AD9736 in the power down state
See SPI and PIN Mode sections for pin description
See SPI and PIN Mode sections for pin description
See SPI and PIN Mode sections for pin description
See SPI and PIN Mode sections for pin description
B14
I120
C14
VREF
D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4
VSSC
D14
IPTAT
E1, F1
E11, E12, F11, F12, G11, G12
CLK-, CLK+
VSSA
E13
IRQ / UNSIGNED
E14
RESET / PD
F13
F14
G13
G14
H1, H2, H3, H4, H11, H12, H13, H14, J1, J2,
J3, J4, J11, J12, J13, J14
K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9,
L10, L11, L12, M3, M4, M5, M6, M9, M10,
M11, M12
K13, K14
CSB / 2x
SDIO / FIFO
SCLK / FSC0
SDO / FSC1
VDD
1.8V Digital supply
VSS
Digital supply ground
DB<13> -, +
Negative, Positive data input bit 13 (MSB), reduced swing LVDS
0, SPI Mode, SPI enabled
1, PIN Mode, SPI disabled, direct pin control
3.3V Digital supply
Negative, Positive data input bit 12, reduced swing LVDS
Negative, Positive data input bit 0 (LSB), reduced swing LVDS
Negative, Positive data input bit 11, reduced swing LVDS
Negative, Positive data input bit 1, reduced swing LVDS
Negative, Positive data input bit 2, reduced swing LVDS
Negative, Positive data input bit 3, reduced swing LVDS
Negative, Positive data input bit 4, reduced swing LVDS
Negative, Positive data input bit 5, reduced swing LVDS
Negative, Positive output clock, reduced swing LVDS
Negative, Positive data input clock, reduced swing LVDS
Negative, Positive data input bit 6, reduced swing LVDS
Negative, Positive data input bit 7, reduced swing LVDS
Negative, Positive data input bit 8, reduced swing LVDS
Negative, Positive data input bit 9, reduced swing LVDS
Negative, Positive data input bit 10, reduced swing LVDS
L1
PIN_MODE
L7, L8, M7, M8, N7, N8, P7, P8
L13, L14
M2, M1
M13, M14
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N6, P6
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
VDD33
DB<12> -, +
DB<0> -, +
DB<11> -, +
DB<1> -, +
DB<2> -, +
DB<3> -, +
DB<4> -, +
DB<5> -, +
DATACLK_OUT -, +
DATACLK_IN -, +
DB<6> -, +
DB<7> -, +
DB<8> -, +
DB<9> -, +
DB<10> -, +
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PDF描述
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