參數(shù)資料
型號(hào)： AD9736
廠商： Analog Devices, Inc.
英文描述： 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述： 14/12/10-Bit，1200 MSPS的D / A轉(zhuǎn)換
文件頁數(shù)： 17/42頁
文件大小： 934K
代理商： AD9736
Preliminary Technical Data
AD9736/AD9735/AD9734
Rev. PrJ | Page 17 of 42
LTRH<2:0> :
: WRITE ->
000
, Set auto update threshold values
REG 07, 08 -> SYNC Controller (SYNC_CNT)
Reading REG 07 & 08 return previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x07
SYNC_CNT1
FIFOSTAT3
FIFOSTAT2
FIFOSTAT1
FIFOSTAT0
VALID
SCHANGE
PHOF<1>
PHOF<0>
0x08
SYNC_CNT2
SSURV
SAUTO
SFLT<3>
SFLT<2>
SFLT<1>
SFLT<0>
RESV’D
STRH<0>
FIFOSTAT<2:0>
: READ ->
Position of FIFO read counter, range from 0 to 7
FIFOSTAT<3>
: READ ->
0, SYNC logic OK
1, Error in SYNC logic
VALID
: READ ->
0, FIFOSTAT<3:0> is not valid yet
1, FIFOSTAT<3:0> is valid after a reset
SCHANGE
: READ ->
0, No change in FIFOSTAT<3:0>
1, FIFOSTAT<3:0> has changed since the previous measurement cycle when SSURV = 1 (surveillance mode active)
PHOF<1:0>
: WRITE ->
00
, Change the readout counter
: READ ->
Current setting of the readout counter (PHOF<1:0>) in surveillance mode (SSURV = 1) after an interrupt
Current calculated optimal readout counter value in AUTO mode (SAUTO = 1)
SSURV
: WRITE ->
0
, The controller stops after completion of the current measurement cycle
1, Continuous measurements are taken and an interrupt is issued if the readout counter drifts beyond the threshold value
SAUTO
: WRITE ->
0
, Readout counter (PHOF<3:0>) is not automatically updated
1, Continuously starts measurement cycles and updates the readout counter according to the measurement
NOTE: SSURV (REG08 Bit 7) must be set to 1 and the SYNC IRQ (REG01 Bit 2) must be set to 0 for AUTO mode
SFLT<3:0>
: WRITE ->
0x0
, Average filter length, FIFOSTAT = FIFOSTAT + Delta FIFOSTAT / 2 ^ SFLT<3:0>, values greater than 12 (0x0C) are clipped to 12
STRH<0>
: WRITE ->
0
, If FIFOSTAT<2:0> = 0 | 7, generate a SYNC interrupt
1, If FIFOSTAT<2:0> = 0 | 1 | 6 | 7, generate a SYNC interrupt
REG 14, 15 -> Analog Control (ANA_CNT)
Reading REG 14 & 15 return previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0E
ANA_CNT1
MSEL<1>
MSEL<0>
TRMBG<2>
TRMBG<1>
TRMBG<0>
0x0F
ANA_CNT2
HDRM<7>
HDRM<6>
HDRM<5>
HDRM<4>
HDRM<3>
HDRM<2>
HDRM<1>
HDRM<0>
MSEL<1:0>
: WRITE ->
00, Mirror roll off frequency control = bypass
01, Mirror roll off frequency control = narrowest bandwidth
10, Mirror roll off frequency control = medium bandwidth
11
, Mirror roll off frequency control = widest bandwidth
NOTE: See plot in the applications section
TRMBG<2:0>
: WRITE ->
000
, Bandgap temperature characteristic trim
NOTE: See plot in the applications section
HDRM<7:0>
: WRITE ->
0xCA
, Output stack headroom control
HDRM<7:4> set reference offset from Vdd3v (vcas centering)
HDRM<3:0> set overdrive (current density) trim (temperature tracking)
Note: Set to 0xCA for optimum performance
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