參數(shù)資料
型號(hào): AD9736
廠商: Analog Devices, Inc.
英文描述: 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述: 14/12/10-Bit,1200 MSPS的D / A轉(zhuǎn)換
文件頁(yè)數(shù): 30/42頁(yè)
文件大?。?/td> 934K
代理商: AD9736
AD9736/AD9735/AD9734
Preliminary Technical Data
APPLICATIONS INFORMATION
Rev. PrJ | Page 30 of 42
FPGA/ASIC DAC DRIVER REQUIREMENTS
To achieve data synchronization using the high speed capability of
the AD9736, ADI recommends the configuration in Figure 35 for
the FPGA/ASIC driving the digital inputs. Using the Double Data
Rate DATACLK_OUT, this configuration will generate the LVDS
DATACLK_IN to drive the AD9736 at the DDR rate. The circuit
also synchronizes the DATACLK_IN and the digital input data
(DB<13:0>) as required by the AD9736. The synchronization
engine in the AD9736 then uses DATACLK_IN to generate the
internal CLOCK SAMPLING SIGNAL to capture the incoming
data via the Manual, Surveillance or Auto mode.
To operate in 2x mode, the circuit in Figure 35 must be modified to
include a divide-by-two block in the DATACLK_OUT path.
Without this additional divider the DATA and DATACLK_IN will
be running 2x too fast. DATACLK_OUT is always DACCLK/2.
Figure 35. Recommended FPGA/ASIC Configuration for Driving AD9736
Digital Inputs, 1x Mode
Figure 36. FPGA/ASIC Timing for Driving AD9736 Digital Inputs, 1x Mode
TIMING ERROR BUDGET
The following components make up the timing error budget for the
AD9736:
1.
2.
AD9736 DATACLK_OUT jitter
AD9736 DATACLK_IN jitter
3.
4.
5.
DB13:0 jitter
DB13:0 skew from data source
DB13:0 receiver skew margin (board + AD9736 internal
delays)
DB13:0 to DATACLK_IN skew from data source
6.
A
C
E
B
D
A
C
B
D
A
B
C
DATACLK_OUT+
DATA1
DATA2
D1
D2
DB
DATACLK_IN+
相關(guān)PDF資料
PDF描述
AD9736-EB 14/12/10-Bit, 1200 MSPS D/A Converters
AD9736BBC 14/12/10-Bit, 1200 MSPS D/A Converters
AD974(中文) 4-Channel, 16-Bit, 200 kSPS Data Acquisition System(4通道,200kSPS16位數(shù)據(jù)采集系統(tǒng))
AD9740 10-Bit, 165 MSPS TxDAC D/A Converter
AD9740-EB 10-Bit, 165 MSPS TxDAC D/A Converter
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