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參數(shù)資料
| 型號： | AD9735 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14/12/10-Bit, 1200 MSPS D/A Converters |
| 中文描述： | 14/12/10-Bit，1200 MSPS的D / A轉換 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 934K |
| 代理商： | AD9735 |
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Preliminary Technical Data
AD9736/AD9735/AD9734
Rev. PrJ | Page 25 of 42
OPERATING THE LVDS CONTROLLER IN SURVEILLANCE
AND AUTO MODE
In surveillance mode, the controller searches for the edges of the
data eye in the same manner as above in the manual mode of
operation and triggers an interrupt if the CLOCK SAMPLING
SIGNAL (CSS) has moved more than the threshold value set by
LTHR<1:0> (REG06, bits 1:0).
There is an internal filter which averages the set-up and hold time
measurements to filter out noise and glitches on the clock lines.
Average Value = ( MHD – MSD ) / 2
New Average = Average Value + ( Delta Average / 2 ^ LFLT<3:0> )
If an accumulating error in the Average Value causes it to exceed
the Threshold value (LTHR<1:0>) an interrupt will be issued.
The maximum allowable value for LFLT<3:0> is 12.
In surveillance mode, the ideal sampling point should first be
found using manual mode and applied to the sample delay
registers. The user should then set the threshold and filter values
depending on how far the CSS signal is allowed to drift before an
interrupt occurs. Then set the surveillance bit high (REG06, bit 7)
and monitor the interrupt signal either via the SPI port read back
(REG01, bit 3) or the IRQ pin.
In auto mode, the same steps should be taken to set up the sample
delay, threshold and filter length. In order to run the controller in
auto mode both the LAUTO (REG06, bit 6) and LSURV (REG06,
bit 7) bits need to be set to 1. In AUTO mode the LVDS interrupt
should be set low (REG01, bit 7) to allow the Sample Delay to be
automatically updated if the threshold value is exceeded.
AD9736 SYNC Logic and
Controller
A FIFO structure is utilized to synchronize the data transfer
between the DACCLK and the DATACLK_IN clock domains. The
SYNC Controller writes data from DB<13:0> into an eight word
memory based on a cyclic write counter clocked by the CLOCK
SAMPLING SIGNAL (CSS) which is a delayed version of
DACCLK_IN. The data is read out of the memory based on a
second cyclic read counter clocked by DACCLK. The eight word
deep FIFO shown in Figure 28 provides sufficient margin to
maintain proper timing under most conditions. The SYNC logic is
designed to prevent the read and write pointers from crossing. If
the timing drifts far enough to require an update of the phase offset
(PHOF<1:0>) two samples will be duplicated or dropped. Figure 29
shows the timing diagram for the SYNC logic.
SYNC LOGIC AND CONTROLLER OPERATION
The relationship between the readout pointer and the write pointer
will initially be unknown since the startup relationship between
DACCLK and DATACLK_IN is unknown. The SYNC logic
measures the relative phase between the two counters with the zero
detect block and the Flip Flop in Figure 5 above. The relative phase
is returned in FIFOSTAT<2:0> (REG07, bits 6:4) and SYNC logic
errors are indicated by FIFOSTAT<3> (REG07, bit 7). If
FIFOSTAT<2:0> returns a value of zero or seven it signifies that the
memory is sampling in a critical state (read and write pointers are
close to crossing). If the FIFOSTAT<2:0> returns a value of 3 or 4 it
signifies the memory is sampling at the optimal state (read and
write pointers are farthest apart). If FIFOSTAT<2:0> returns a
critical value the pointer can be adjusted with the phase offset
PHOF<1:0> (REG07, bits 1:0). Due to the architecture of the FIFO
the phase offset can only adjust the read pointer in steps of two.
OPERATING IN MANUAL MODE
Allow DACCLK and DATACLK_IN to stabilize then enable FIFO
mode (REG00, bit 2). Read FIFOSTAT<2:0> (REG07, bits 6:4) to
determine if adjustment is needed. For example if FIFOSTAT<2:0>
= 6 the timing is not yet critical but it is not optimal. To return to
an optimal state (FIFOSTAT<2:0> = 4) the PHOF<1:0> (REG07,
bits 1:0) needs to be set to 1. Setting PHOF<1:0> = 1 effectively
increments the read pointer by 2. This causes the write pointer
value to be captured two clocks later decreasing FIFOSTAT<2:0>
from 6 to 4.
Figure 28. SYNC Logic Block Diagram
Memory
DAC<13:0>
DB<13:0>
M0
M7
Counter
Counter
Adder
CSS
DACCLK
PHOF<1:0>
ZD
FF
FIFOSTAT<2:0>
8 Word
Write
Read
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