參數(shù)資料
型號: AD9735
廠商: Analog Devices, Inc.
英文描述: 14/12/10-Bit, 1200 MSPS D/A Converters
中文描述: 14/12/10-Bit,1200 MSPS的D / A轉(zhuǎn)換
文件頁數(shù): 18/42頁
文件大?。?/td> 934K
代理商: AD9735
AD9736/AD9735/AD9734
Preliminary Technical Data
Rev. PrJ | Page 18 of 42
REG 17, 18, 19, 20, 21 -> Built-in Self Test Control (BIST_CNT)
Reading REG17, 18, 19, 20 & 21 return previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x11
BIST_CNT
SEL<1>
SEL<0>
SIG_READ
LVDS_EN
SYNC_EN
CLEAR
0x12
BIST<7:0>
BIST<7>
BIST<6>
BIST<5>
BIST<4>
BIST<3>
BIST<2>
BIST<1>
BIST<0>
0x13
BIST<15:8>
BIST<15>
BIST<14>
BIST<13>
BIST<12>
BIST<11>
BIST<10>
BIST<9>
BIST<8>
0x14
BIST<23:16>
BIST<23>
BIST<22>
BIST<21>
BIST<20>
BIST<19>
BIST<18>
BIST<17>
BIST<16>
0x15
BIST<31:24>
BIST<31>
BIST<30>
BIST<29>
BIST<28>
BIST<27>
BIST<26>
BIST<25>
BIST<24>
SEL<1:0>
: WRITE ->
00, Write result of the LVDS Phase 1 BIST to BIST<31:0>
01, Write result of the LVDS Phase 2 BIST to BIST<31:0>
10, Write result of the SYNC Phase 1 BIST to BIST<31:0>
11, Write result of the SYNC Phase 2 BIST to BIST<31:0>
SIG_READ
: WRITE ->
0, No action
1, Enable BIST signature readback
LVDS_EN
: WRITE->
0, No action
1, Enable LVDS BIST
SYNC_EN
: WRITE ->
0, No Action
1, Enable SYNC BIST
CLEAR
: WRITE ->
0, No Action
1, Clear all BIST registers
BIST<31:0>
: READ ->
Results of the Built-in Self Test
REG 22 -> Controller Clock Pre-divider (CCLK_DIV)
Reading REG 22 returns previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x16
CCLK_DIV
RESV’D
RESV’D
RESV’D
RESV’D
CCD<3>
CCD<2>
CCD<1>
CCD<0>
CCD<3:0>
: WRITE ->
0x0
, Controller Clock = DACCLK / 16
0x1, Controller Clock = DACCLK / 32
0x2, Controller Clock = DACCLK / 64 …
0xF, Controller Clock = DACCLK / 524288
NOTE: The 100MHz to 1.2GHz DACCLK must be divided to less than 10MHz for correct operation. CCD<3:0> must be programmed to
divide the DACCLK so that this relationship is not violated. Controller Clock = DACCLK / ( 2 ^ ( CCD<3:0> + 4 ))
REG 31 -> VERSION
Reading REG 31 returns previously written values for all defined register bits unless otherwise noted. Reset value in
bold
text.
ADR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x1F
VERSION
VER<5>
VER<4>
VER<3>
VER<2>
VER<1>
VER<0>
RES10
RES12
VER<5:0>
: READ ->
Version number (part ID), 00001, Revision 1, initial release
RES10 (msb)
RES12 (lsb)
: READ ->
00, 14-bit DAC
01, 12-bit DAC
10, 10-bit DAC
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