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參數(shù)資料
| 型號： | AD9709-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, 125 MSPS Dual TxDAC D/A Converter |
| 中文描述： | 8位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 466K |
| 代理商： | AD9709-EB |
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REV. 0
AD9709
–12–
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter-
leaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
IQSEL
IQWRT
DAC1
LATCH
DAC1
INTERLEAVED
DATA IN, PORT 1
DEINTERLEAVED
DATA OUT
IQCLK
IQRESET
DAC2
LATCH
DAC2
2
PORT 1
INPUT
LATCH
PORT 2
INPUT
LATCH
Figure 25. Latch Structure in Interleaved Mode
Timing specifications for interleaved mode are given in Figures
26 and 27.
DATA IN
IQWRT
IQCLK
IOUTA
OR
IOUTB
t
LPW
t
PD
t
S
t
H
t
H
*
IQSEL
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY
Figure 26. Interleaved Mode Timing
D1
D2
D3
D4
D5
INTERLEAVED
DATA
xx
xx
D1
D2
D3
D4
xx
IQSEL
IQWRT
IQRESET
DAC OUTPUT
PORT 1
DAC OUTPUT
PORT 2
IQCLK
Figure 27. Interleaved Mode Timing
The digital inputs are CMOS-compatible with logic thresholds,
V
THRESHOLD
, set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2 (
±
20%)
The internal digital circuitry of the AD9709 is capable of oper-
ating over a digital supply range of 3 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high-level voltage of the
TTL drivers V
OH
(MAX). A DVDD of 3 V to 3.3 V will typically
ensure proper compatibility with most TTL logic families. Fig-
ure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the exception
that it contains an active pull-down circuit, thus ensuring that
the AD9709 remains enabled if this input is left disconnected.
Since the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9709 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low-
value resistor network (i.e., 20
to 100
) between the AD9709
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high-data update
rates, stripline techniques with proper impedance and termina-
tion resistors should be considered to maintain “clean” digital
inputs.
The external clock driver circuitry should provide the AD9709
with a low-jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed
waveform. Thus, the clock input should be driven by the fastest
logic family suitable for the application.
DVDD
DIGITAL
INPUT
Figure 28. Equivalent Digital Input
Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the
effective clock duty cycle and, subsequently, cut into the required
data setup and hold times.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9709-EBZ | 功能描述:BOARD EVAL FOR AD9709 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9709-EBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 125 MSPS, Dual TxDAC Digital-to-Analog Converter |
| AD9712 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-BIT, 100MSPS D/A CONVERTERS |
| ad97128bsq/883b | 制造商:Analog Devices 功能描述: |
| AD9712AJN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
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