參數(shù)資料
型號： AD9644BCPZRL7-80
廠商： Analog Devices Inc
文件頁數(shù)： 35/44頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS 3V 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 460mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，雙極
AD9644
Data Sheet
Rev. C | Page 40 of 44
JESD204A Device Identification Number (DID)
(Register 0x64)
Bits[7:0]—Serial Device Identification (DID) Number
JESD204A Bank Identification Number (BID)
(Register 0x65)
Bits[7:4]—Open
Bits[3:0]—Serial Bank Identification (DID) Number
JESD204A Lane Identification Number (LID) for Lane 0
(Register 0x66)
Bits[7:5]—Open
Bits[4:0]—Serial Lane Identification (LID) Number for
Lane 0.
JESD204A Lane Identification Number (LID) for Lane 1
(Register 0x67)
Bits[7:5]—Open
Bits[4:0]—Serial Lane Identification (LID) Number for
Lane 1.
JESD204A Scrambler (SCR) and Lane Configuration
Registers (Register 0x6E)
Bit 7—Enable Serial Scrambler Mode
Setting this bit high enables the scrambler (SCR = 1).
Bits[6:1]—Open
Bit[0]—Serial Lane Control.
00000: one lane per link (L = 1).
00001: two lanes per link (L = 2).
00010: 11111—reserved.
JESD204A Number of Octets Per Frame (F)
(Register 0x6F—Read Only)
Bits[7:0]—Number of Octets per Frame (F)
The readback from this register is calculated from the following
equation: F = (M × 2)/L
Valid values for F for the AD9644 are:
F = 2, with M = 1 and L = 1
F = 4, with M = 2 and L = 1
F = 2, with M = 2 and L = 2
JESD204A Number of Frames Per Multiframe
(Register 0x70)
Bits[7:5]—Reserved
Bits[4:0]—Number of Frames per Multiframe (K).
JESD204A Number of Converters Per Link (M)
(Register 0x71)
Bits[7:1]—Reserved
Bit 0—Number of Converters per Link per Device (M).
0: link connected to one ADC. Only primary input used (M = 1).
1: link connected to two ADCs. Primary and secondary inputs
used (M = 2).
JESD204A ADC Resolution (N) and Control Bits Per
Sample (CS) (Register 0x72)
Bits[7:6]—Number of Control Bits per Sample (CS)
00: no control bits sent per sample (CS = 0).
01: one control bits sent per sample—overrange bit enabled.
(CS = 1).
10: two control bits sent per sample—overflow/underflow bits
enabled (CS = 2).
11: unused.
Bit 5—Open
Bits[4:0]—Converter Resolution (N)
Read only bits showing the converter resolution (reads back 13
(0xD) for 14-bit resolution).
JESD204A Total Bits Per Sample (N’) (Register 0x73)
Bits[7:5]—Open
Bits[4:0]—Total Number of Bits per Sample (N’)
Read only bits showing the total number of bits per sample—1
(reads back 15 (0xF) for 16 bits per sample).
JESD204A Samples Per Converter (S) Frame Cycle
(Register 0x74)
Bits[7:5]—Open
Bits[4:0]—Samples per Converter Frame Cycle (S)
Read only bits showing the number of samples per converter
frame cycle 1 (reads back 0 (0x0) for 1 sample per converter
frame).
JESD204A HD and CF Configuration (Register 0x75)
Bit 7—Enable High Density Format (Read Only)
Read only bit—always 0 in the AD9644.
Bits[6:5]—Reserved
Bits[4:0]—Number of Control Words per Frame Clock
Cycle per Link (CF)
Read only bits—reads back 0x0 for the AD9644.
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