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參數資料
| 型號： | AD9643BCPZRL7-210 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數： | 7/36頁 |
| 文件大?。?/td> | 1659K |
| 代理商： | AD9643BCPZRL7-210 |
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AD9643
Rev. A | Page 15 of 36
Pin No.
Mnemonic
Type
Description
14
B D4+/D5+
Output
Channel B LVDS Output Data 4/Data 5—True.
15
B D6/D7
Output
Channel B LVDS Output Data 6/Data 7—Complement.
16
B D6+/D7+
Output
Channel B LVDS Output Data 6/Data 7—True.
17
B D8/D9
Output
Channel B LVDS Output Data 8/Data 9—Complement.
18
B D8+/D9+
Output
Channel B LVDS Output Data 8/Data 9—True.
20
B D10/D11
Output
Channel B LVDS Output Data 10/Data 11—Complement.
21
B D10+/D11+
Output
Channel B LVDS Output Data 10/Data 11—True.
22
B D12/D13
(MSB)
Output
Channel B LVDS Output Data 12/Data 13—Complement.
23
B D12+/D13+
(MSB)
Output
Channel B LVDS Output Data 12/Data 13—True.
26
A D0/D1 (LSB)
Output
Channel A LVDS Output Data 0/Data 1—Complement.
27
A D0+/D1+ (LSB)
Output
Channel A LVDS Output Data 0/Data 1—True.
29
A D2/D3
Output
Channel A LVDS Output Data 2/Data 3—Complement.
30
A D2+/D3+
Output
Channel A LVDS Output Data 2/Data 3—True.
31
A D4/D5
Output
Channel A LVDS Output Data 4/Data 5—Complement.
32
A D4+/D5+
Output
Channel A LVDS Output Data 4/Data 5—True.
33
A D6/D7
Output
Channel A LVDS Output Data 6/Data 7—Complement.
34
A D6+/D7+
Output
Channel A LVDS Output Data 6/Data 7—True.
35
A D8/D9
Output
Channel A LVDS Output Data 8/Data 9—Complement.
36
A D8+/D9+
Output
Channel A LVDS Output Data 8/Data 9—True.
38
A D10/D11
Output
Channel A LVDS Output Data 10/Data 11—Complement.
39
A D10+/D11+
Output
Channel A LVDS Output Data 10/Data 11—True.
40
A D12/D13
(MSB)
Output
Channel A LVDS Output Data 12/Data 13—Complement.
41
A D12+/D13+
(MSB)
Output
Channel A LVDS Output Data 12/Data 13—True.
43
OR+
Output
Channel A/Channel B LVDS Overrange Output—True.
42
OR
Output
Channel A/Channel B LVDS Overrange Output—Complement.
25
DCO+
Output
Channel A/Channel B LVDS Data Clock Output—True.
24
DCO
Output
Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45
SCLK
Input
SPI Serial Clock.
44
SDIO
Input/Output
SPI Serial Data Input/Output.
46
CSB
Input
SPI Chip Select (Active Low).
Output Enable and Power-Down
47
OEB
Input
Output Enable Input (Active Low).
48
PDWN
Input
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-
down or standby (see Table 14).
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