參數(shù)資料
型號： AD9643BCPZRL7-210
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 2-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù)： 20/36頁
文件大?。?/td> 1659K
代理商： AD9643BCPZRL7-210
AD9643
Rev. A | Page 27 of 36
DIGITAL OUTPUTS
The AD9643 output drivers can be configured for either ANSI
LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD9643 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB pin
or through the SPI interface. If the OEB pin is low, the output
data drivers are enabled. If the OEB pin is high, the output data
drivers are placed in a high impedance state. This OEB function
is not intended for rapid access to the data bus. Note that OEB
is referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI interface, the data outputs of each channel
can be independently three-stated by using the output enable
bar bit (Bit 4) in Register 0x14. Because the output data is
interleaved, if only one of the two channels is disabled, the output
data of the remaining channel is repeated in both the rising and
falling output clock cycles.
Timing
The AD9643 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9643.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9643 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9643 also provides data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows a
graphical timing diagram of the AD9643 output modes.
Table 11. Output Data Format
Input (V)
VIN+ VIN,
Input Span = 1.75 V p-p (V)
Offset Binary Output Mode
Twos Complement Mode (Default)
OR
VIN+ VIN
<–0.875
00 0000 0000 0000
10 0000 0000 0000
1
VIN+ VIN
–0.875
00 0000 0000 0000
10 0000 0000 0000
0
VIN+ VIN
0
10 0000 0000 0000
00 0000 0000 0000
0
VIN+ VIN
+0.875
11 1111 1111 1111
01 1111 1111 1111
0
VIN+ VIN
>+0.875
11 1111 1111 1111
01 1111 1111 1111
1
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