參數(shù)資料
型號(hào)： AD9643BCPZRL7-210
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 2-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 1659K
代理商： AD9643BCPZRL7-210
AD9643
Rev. A | Page 25 of 36
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9643.
The full-scale input range can be adjusted by varying the
reference voltage via SPI. The input span of the ADC tracks
reference voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9643 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 51) and require no external bias. If the inputs are
floated, the CLK pin is pulled low to prevent spurious clocking.
0
96
36-
0
55
AVDD
CLK+
4pF
CLK–
0.9V
Figure 51. Simplified Equivalent Clock Input Circuit
Clock Input Options
The AD9643 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 52 and Figure 53 show two preferable methods for
clocking the AD9643 (at clock rates of up to 625 MHz). A low
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9643 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
the clock from feeding through to other portions of the AD9643
while preserving the fast rise and fall times of the signal, which
are critical to low jitter performance.
390pF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
0
96
36
-05
6
Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz)
390pF
CLOCK
INPUT
1nF
25
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
09
636
-05
7
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 54. The AD9510, AD9511, AD9512,
ADCLK925 clock drivers offer excellent jitter performance.
100
0.1F
240
PECL DRIVER
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
ADC
09
636-
05
8
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
offer excellent jitter performance.
100
0.1F
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDS DRIVER
ADC
096
36-
059
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9643 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
The AD9643 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
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AD9644-80KITZ 功能描述:BOARD EVALUATION FOR AD9644 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
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