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| 型號： | AD9639BCPZRL-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12B 170MSPS QUAD 72LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 210M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.39W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極 |
| 其它名稱： | AD9639BCPZRL-170DKR |
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Data Sheet
AD9639
Rev. B | Page 17 of 36
THEORY OF OPERATION
The AD9639 architecture consists of a differential input buffer and
a front-end sample-and-hold amplifier (SHA) followed by a pipe-
lined switched-capacitor ADC. The quantized outputs from each
stage are combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to operate
on a new input sample while the remaining stages operate on pre-
ceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output of
the pipeline ADC is put into its final serial format by the data
serializer, encoder, and CML drivers block. The data rate multiplier
creates the clock used to output the high speed serial data at the
CML outputs.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9639 is a differential buffer. This
input is optimized to provide superior wideband performance
and requires that the analog inputs be driven differentially. SNR
and SINAD performance degrades if the analog input is driven
with a single-ended signal.
For best dynamic performance, the source impedances driving
VIN + x and VIN x should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. A small resistor in series
with each input can help to reduce the peak transient current
injected from the output stage of the driving source.
In addition, low Q inductors or ferrite beads can be placed on
each leg of the input to reduce high differential capacitance at
the analog inputs and, therefore, achieve the maximum band-
width of the ADC. The use of low Q inductors or ferrite beads is
required when driving the converter front end at high IF
frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the AN-827
Application Note and the Analog Dialogue article “Transformer-
Coupled Front-End for Wideband A/D Converters” (Volume 39,
Number 2, April 2005) for more information on this subject. In
general, the precise values depend on the application.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9639, the default input span is 1.25 V p-p. To configure the ADC
for a different input span, see the VREF register (Address 0x18).
For the best performance, an input span of 1.25 V p-p or greater
should be used (see Table 15 for details).
Differential Input Configurations
The AD9639 can be driven actively or passively; in either case,
optimum performance is achieved by driving the analog input
differentially. For example, using the ADA4937 differential ampli-
fier to drive the AD9639 provides excellent performance and a
flexible interface to the ADC for baseband and second Nyquist
(~100 MHz IF) applications (see Figure 36 and Figure 37). In either
application, use 1% resistors for good gain matching. Note that the
dc-coupled configuration shows some degradation in spurious per-
formance. For more information, consult the ADA4937 data sheet.
SIGNAL
GENERATOR
+VS
–VS
3.3V
205
200
10k
62
10k
27
0.1F
1.25V p-p
ADA4937
G = UNITY
VIN + x
VIN – x
OPTIONAL C
33
24
0.1F
R
C
AVDD
DRVDD
1.8V
AD9639
ADC INPUT
IMPEDANCE
1.65V
VOCM
07973-
090
Figure 36. Differential Amplifier Configuration for AC-Coupled Baseband Applications
SIGNAL
GENERATOR
+VS
–VS
3.3V
205
200
62
27
0.1F
1.25V p-p
ADA4937
G = UNITY
VIN + x
VIN – x
OPTIONAL C
33
24
R
C
AVDD
DRVDD
1.8V
AD9639
ADC INPUT
IMPEDANCE
VOCM
VCM x
1.4V
07973-
091
Figure 37. Differential Amplifier Configuration for DC-Coupled Baseband Applications
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