參數(shù)資料
型號(hào)： AD9639BCPZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12B 170MSPS QUAD 72LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 210M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.39W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9639
Data Sheet
Rev. B | Page 26 of 36
–200
–100
0
100
200
–30
–10
0
10
30
–0.5
0.5
TIME (ps)
ULS
400
600
200
0
–200
–400
–600
VO
L
T
A
G
E
(
m
V
)
HEIGHT1: EYE DIAGRAM
TIE1: HISTOGRAM
TJ@BERI: BATHTUB
1
+
500
600
400
300
200
100
0
HI
T
S
100
10–2
10–4
10–6
10–8
10–10
10–12
10–14
BE
R
3
+
2
+
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL: 12000: 80091
(y1)
(y2)
(y)
–375.023m
+409.847m
+784.671m
07
97
3-
0
9
4
Figure 59. Digital Outputs Data Eye with Trace Lengths Less Than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
–200
–100
0
100
200
–50
0
50
TIME (ps)
400
600
200
0
–200
–400
–600
VO
LT
AG
E
(
m
V
)
250
300
200
150
100
50
0
HI
T
S
HEIGHT1: EYE DIAGRAM
TIE1: HISTOGRAM
0
–0.5
0.5
ULS
BE
R
TJ@BERI: BATHTUB
3
+
2
+
1
+
(y1)
(y2)
(y)
–402.016m
+398.373m
+800.389m
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL 8000: 40044
0
797
3-
0
95
100
10–2
10–4
10–6
10–8
10–10
10–12
10–14
Figure 60. Digital Outputs Data Eye with Trace Lengths Greater Than 12 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
Figure 59 shows an example of the digital output (default) data
eye and a time interval error (TIE) jitter histogram with trace
lengths less than 6 inches on standard FR-4 material. Figure 60
shows an example of trace lengths exceeding 12 inches on stan-
dard FR-4 material. Note that the TIE jitter histogram reflects
the decrease of the data eye opening as the edge deviates from
the ideal position. It is the user’s responsibility to determine
whether the waveforms meet the timing budget of the design
when the trace lengths exceed 6 inches.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Address 0x15 in Table 15). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. See the Memory Map section
for more details.
The format of the output data is offset binary by default.
Table 10 provides an example of this output coding format.
To change the output data format to twos complement or gray
code, see the Memory Map section (Address 0x14 in Table 15).
Table 10. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 1.25 V p-p (V)
Digital Output Offset
Binary ([D11:D0])
4095
+0.625
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000305
0111 1111 1111
0
0.625
0000 0000 0000
The lowest typical clock rate is 100 MSPS. For clock rates slower
than 100 MSPS, the user can set Bit 3 to 0 in the serial control
register (Address 0x21 in Table 15). This option allows the user
to adjust the PLL loop bandwidth to use clock rates as low as
50 MSPS.
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