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| 型號： | AD9600ABCPZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 125MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9600
Rev. B | Page 40 of 72
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map registers table (Table 22) has eight
bit locations. The memory map is divided into four sections: the
chip configuration registers (Address 0x00 to Address 0x02), the
channel index and transfer registers (Address 0x05 and Address
0xFF), the ADC functions registers (Address 0x08 to Address
0x25), and the digital feature control registers (Address 0x100 to
Address 0x11B).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The (MSB) Bit 7 column is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a default value of 0xC0, meaning that
Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the
default reference selection setting. The default value uses a 2.0 V
peak-to-peak reference. For more information on this function and
others, see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This application note details the functions controlled
by Register 0x00 to Register 0xFF. The remaining registers
(from Register 0x100 to Register 0x11B) are documented in
the Memory Map Register Description section.
Open Locations
All address and bit locations that are not included in Table 22
are currently not supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
When the AD9600 comes out of a reset, critical registers are
loaded with default values. The default values for the registers
are given in the memory map registers table (Table 22).
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit (Bit 0 of Register 0xFF) is set. The
internal update takes place when the transfer bit is set, and the
bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be individually programmed for each channel.
In these cases, channel address locations are internally
duplicated for each channel. These registers are designated as
local registers in Table 22 and can be accessed by setting the
appropriate Channel A or Channel B bits in Register 0x05. If
both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are
set during an SPI read cycle, the part returns the value for
Channel A.
On the other hand, registers that are designated as global registers
in Table 22 affect the entire part or the channel features for which
independent settings are not allowed between the channels. The
settings in Register 0x05 do not affect the global registers.
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