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    參數(shù)資料
    型號: AD9575ARUZPEC
    廠商: ANALOG DEVICES INC
    元件分類: 時鐘產(chǎn)生/分配
    英文描述: Network Clock Generator, Two Outputs, TSSOP 4.4 MM, No of Pins: 16
    中文描述: OTHER CLOCK GENERATOR, PDSO16
    封裝: 4.4 X 5 MM, ROHS COMPLIANT, MO-153AB, TSSOP-16
    文件頁數(shù): 12/16頁
    文件大?。?/td> 359K
    代理商: AD9575ARUZPEC
    AD9575
    Rev. A | Page 5 of 16
    OUTPUT FREQUENCY SELECT
    Minimum (min) and maximum (max) values are given over the full VS and TA (40°C to +85°C) variation.
    Table 4.
    Parameter
    Min
    Typ
    Max
    Unit
    Test Conditions/Comments
    Select Pins (SEL0/SEL1)
    Logic 1 Voltage
    0.83 × VS + 0.2
    V
    Logic 0 Voltage
    0.33 × VS 0.2
    V
    Logic 1 Current
    190
    μA
    Pull-up to VS
    Logic 0 Current
    150
    μA
    Pull-down to GND
    CLOCK OUTPUTS
    Typical (typ) values are given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are
    given over the full VS and TA (40°C to +85°C) variation.
    Table 5.
    Parameter
    Min
    Typ
    Max
    Unit
    Test Conditions/Comments
    LVDS CLOCK OUTPUT
    Termination = 100 Ω differential; default
    Output Frequency
    312.5
    MHz
    Differential Output Voltage (VOD)
    250
    340
    450
    mV
    See Figure 2 for definition
    Delta VOD
    25
    mV
    Output Offset Voltage (VOS)
    1.125
    1.25
    1.375
    V
    Delta VOS
    25
    mV
    Short-Circuit Current (ISA, ISB)
    14
    24
    mA
    Output shorted to GND
    Duty Cycle
    45
    50
    55
    %
    LVPECL CLOCK OUTPUT
    Output Frequency
    312.5
    MHz
    Output High Voltage (VOH)
    VS 1.5
    VS 1.05
    VS 0.8
    V
    Output Low Voltage (VOL)
    VS 2.5
    VS 1.75
    VS 1.7
    V
    Differential Output Voltage (VOD)
    430
    640
    800
    mV
    See Figure 2 for definition
    Duty Cycle
    45
    50
    55
    %
    LVCMOS CLOCK OUTPUT
    Output Frequency
    62.5
    MHz
    Output High Voltage (VOH)
    VS 0.1
    V
    Output Low Voltage (VOL)
    0.1
    V
    Duty Cycle
    45
    50
    55
    %
    TIMING CHARACTERISTICS
    Table 6.
    Parameter
    Min
    Typ
    Max
    Unit
    Test Conditions/Comments
    LVDS
    Termination = 100 Ω differential; CLOAD = 0 pF;
    CAC = 0.1 μF
    Output Rise Time, tRL
    150
    200
    300
    ps
    20% to 80%, measured differentially
    Output Fall Time, tFL
    150
    200
    300
    ps
    80% to 20%, measured differentially
    LVPECL
    Termination = 200 Ω to GND; CLOAD = 0 pF;
    CAC = 0.1 μF
    Output Rise Time, tRL
    180
    250
    300
    ps
    20% to 80%, measured differentially
    Output Fall Time, tFL
    180
    250
    300
    ps
    80% to 20%, measured differentially
    LVCMOS
    Termination = 50 Ω to 0 V; CLOAD = 5 pF;
    CAC = 0.1 μF
    Output Rise Time, tRC
    0.50
    0.70
    1.10
    ns
    20% to 80%
    Output Fall Time, tFC
    0.50
    0.70
    1.10
    ns
    80% to 20%
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