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參數(shù)資料
| 型號： | AD9552BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN LP 32LFCSP |
| 設(shè)計資源： | Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | CMOS，晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
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AD9552
Data Sheet
Rev. E | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Y4
Y5
A0
A1
A2
RESET
VDD
LDO
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
X
T
A
L
X
T
A
L
RE
F
S
CL
K
S
DI
O
OU
TS
E
L
FI
L
T
ER
Y3
Y2
Y1
Y0
V
DD
OU
T1
G
ND
TOP VIEW
(Not to Scale)
AD9552
07806-
002
OU
T1
GND
OUT2
VDD
LOCKED
LDO
VDD
LDO
OUT2
CS
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
1
12
13
14
15
16
32
31
30
29
28
27
26
25
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
29, 30, 31,
32, 1, 2
Y0, Y1, Y2, Y3, Y4,
Y5
I
Control Pins. These pins select preset values for the PLL feedback divider and the OUT1
dividers based on the input reference frequency selected via the A[0:2] pins and have
internal 100 kΩ pull-up resistors.
3, 4, 5
A0, A1, A2
I
Control Pins. These pins select the input reference frequency and have internal 100 kΩ pull-
up resistors.
6
RESET
I
Digital Input, Active High. Resets internal logic to default states. This pin has an internal
100 kΩ pull-up resistor, so the default state of the device is reset.
7, 18, 21, 28
VDD
P
Power Supply Connection: 3.3 V Analog Supply.
8, 17, 19
LDO
P/O
LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to
ground.
9, 10
XTAL
I
Crystal Resonator Input. Connect a crystal resonator across these pins.2
11
REF
I
Reference Clock Input. Connect this pin to an active clock input signal, or connect it to VDD
when using a crystal resonator across the XTAL pins.
12
CS
I
Digital Input, Active Low, Chip Select.
13
SCLK
I
Serial Data Clock.
14
SDIO
I/O
Digital Serial Data Input/Output.
15
OUTSEL
I
Logic 0 selects LVDS and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2
when the outputs are not under SPI port control. Can be overridden via the programming
registers. This pin has an internal 100 kΩ pull-up resistor.
16
FILTER
I/O
Loop Filter Node for the PLL. Connect an external 12 nF capacitor from this pin to Pin 17 (LDO).
20
LOCKED
O
Active High Locked Status Indicator for the PLL.
26, 22
OUT1, OUT2
O
Complementary Square Wave Clocking Outputs.
27, 23
OUT1, OUT2
O
Square Wave Clocking Outputs.
24, 25
GND
P
Analog Ground.
EP
Exposed Die Pad
The exposed die pad must be connected to GND.
1 I = input, I/O = input/output, O = output, P = power, P/O = power/output.
2 When no crystal is in use, leave these pins floating. The terminations are handled by internal circuitry.
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| AD9552BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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