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參數(shù)資料
| 型號(hào)： | AD9551BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN TRANSLATOR 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9551BCPZ-REEL7DKR |
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AD9551
Rev. B | Page 21 of 40
HOLDOVER MODE
In the absence of both input references, the device enters holdover
mode. Holdover is a secondary function that is provided by the
input PLL. Because the DCXO has an external crystal as its fre-
quency source, it continues to operate in the absence of the input
reference signals. When the device switches to holdover, the DCXO
is held at the frequency at which it was operating just prior to
switchover. The device continues operating in this mode until
a reference signal becomes available; the device then exits holdover
mode, and the input PLL resynchronizes with the active reference.
JITTER TOLERANCE
Jitter tolerance is the ability of the AD9551 to maintain lock in the
presence of sinusoidal jitter. The AD9551 meets the DS1 reference
input jitter tolerance mask per Telcordia GR-1244-CORE (see
Figure 22). The acceptable jitter tolerance is the region above the
mask.
10
1
JI
TT
E
R
(
U
Ip-
p)
0.1
10
100
1k
10k
100k
JITTER FREQUENCY (Hz)
07
80
5-
03
1
EXTERNAL TIMING MASK
LINE TIMING MASK
Figure 22. Jitter Tolerance
EXTERNAL LOOP FILTER CAPACITOR
The output PLL loop filter requires the connection of an external
capacitor from LF (Pin 17) to LDO_VCO (Pin 22). The value of
the external capacitor depends on the operating mode (normal
or 19.44 MHz). Normal mode requires a 12 nF capacitor that sets
the loop bandwidth at approximately 70 kHz and ensures loop
stability over the intended operating parameters of the device.
The 19.44 MHz mode requires a 100 nF capacitor, along with
a change in the output PLL charge pump current to 25 μA, via
Register 0x0A. This establishes similar loop bandwidth and
stability criteria as found in normal mode.
Note that the 19.44 MHz mode does not function properly
unless the user changes the output PLL charge pump current
from its default setting to 25 μA.
OUTPUT/INPUT FREQUENCY RELATIONSHIP
Following are the three equations that define the frequency
at OUT1 and OUT2 (fOUT1 and fOUT2, respectively). Note that
in the equations throughout this datasheet, the subscripted x
indicates A or B.
+
=
)
(
2
1
x
REF
IF
MOD
FRAC
N
K
f
x
1)
+
=
1
0
MOD
FRAC
IF
OUT1
P
N
f
2)
2
OUT1
OUT2
P
f
=
3)
where:
fREFA and fREFB are the input reference frequency, with the
subscripted A or B indicating REFA or REFB, respectively.
fIF is the frequency at the input of the output PLL’s PDF.
P0 and P1 are OUT1 divider values.
P2 is the OUT2 divider value.
K is the input mode scale factor.
NA, NB, FRACA, FRACB, MODA, and MODB are the input reference
divider values, with the A or B subscript indicating REFA or REFB,
respectively.
N, FRAC, and MOD are the feedback divider values for the
output PLL.
The various dividers have the following constraints:
{
}
∈
x
N
63
,
2
,
1
L
with SDM disabled
{
}
∈
x
N
63
,
4
,
3
L
with SDM active
{
}
∈
287
,
524
,
287
,
524
,
288
,
524
L
x
FRAC
{
}
∈
x
MOD
287
,
524
,
2
,
1
L
{
}
255
,
65
,
64
L
N
∈
{
}
∈
FRAC
575
,
048
,
1
,
1
,
0
L
{
}
575
,
048
,
1
,
2
,
1
L
MOD
∈
{
}
∈
0
P
11
,
5
,
4
L
{
}
∈
1
P
63
,
2
,
1
L
{
}
∈
2
P
63
,
2
,
1
L
The VCO imposes the following constraint on fIF:
MHz
4050
MHz
3350
+
≤
+
MOD
FRAC
IF
MOD
FRAC
N
f
N
The input frequencies (fREFA and fREFB) must satisfy the following
relationship:
=
)
(
1
B
REF
A
REF
MOD
FRAC
f
FRAC
f
B
A
+
+
2
)
(
2
B
A
N
MOD
N
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9552 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Oscillator Frequency Upconverter |
| AD9552/PCBZ | 功能描述:BOARD EVALUATION FOR AD9552 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9552BCPZ | 功能描述:IC PLL CLOCK GEN LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9552BCPZ | 制造商:Analog Devices 功能描述:IC PLL CLOCK GENERATOR 112.5MHZ LFCSP-32 |
| AD9552BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN LP 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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