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參數(shù)資料
| 型號(hào)： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 37/76頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 42 of 76
POWER-UP
POWER-ON RESET
On initial power-up, it is recommended that the user apply a
RESET pulse, at least 75 ns in duration, on Pin 59 after both of
the following two conditions are met:
The 3.3 V supply is greater than 2.35 V ± 0.1 V.
The 1.8 V supply is greater than 1.4 V ± 0.05 V.
The high-to-low transition of the RESET pulse is the active
edge of the pulse and therefore the user is afforded the option
of holding RESET high during power–up.
Less than 1 ns after RESET goes high, the S1 to S4 configuration
pins go high impedance and remain high impedance until RESET
is deactivated. This allows strapping and configuration during
RESET.
Because of this reset sequence, external power supply sequenc-
ing is not critical.
PROGRAMMING SEQUENCE
The following sequence should be used when initializing the
AD9549:
1. Apply power. After the power supplies reach a threshold and
stabilize, it is recommended that an active high pulse be
asserted on the RESET pin (Pin 59), initiating a hard reset.
2. It is important to be sure that the desired configuration
registers have single-tone mode set (Register 0x0100, Bit 5)
and that the close loop bit (Register 0x0100[0]) is cleared.
If the close loop bit is set on initial loading, the AD9549
attempts to lock the loop before it has been configured.
3. When the registered are loaded, the OOL (out of limits)
and LOR (loss of reference) can be monitored to ensure
that a valid reference signal is present on REFA or REFB.
If a valid reference is present, Register 0x0100 can be
reprogrammed to clear single-tone mode and lock the loop.
4. Automatic holdover mode can then be used to make the
AD9549 immune to any disturbance on the reference inputs.
Use the following sequence when changing frequencies in the
AD9549:
1. Open the loop and enter single-tone mode via
Register 0x0100.
2. Enter the new register settings.
3. Write 0x1E to Register 0x0012.
4. When the registers are loaded, the OOL (out of limits) and
LOR (loss of reference) can be monitored to ensure that
a valid reference signal is present on REFA or REFB.
5. If a valid reference is present, Register 0x0100 can be repro-
grammed to clear single-tone mode and lock the loop.
6. Automatic holdover mode can then be used to make the
AD9549 immune to any disturbance on the reference
inputs.
Note the following:
Attempting to lock the loop without a valid reference can
put the AD9549 into a state that requires a reset, or at a
minimum, writing 0xFF to Register 0x0012.
Automatic holdover mode is not available unless the loop
has been successfully closed.
If the user desires to open and close the loop manually, it is
recommended that 0x1E to be written to Register 0x0012
prior to closing the loop again.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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