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| 型號(hào)： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 10 of 76
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
A
V
DD
P
F
D_V
RB
P
F
D_V
RT
P
F
D_RS
E
T
V
DD
A
V
DD
A
V
DD
A
V
DD
SYSC
L
K
SYSC
L
K
B
A
V
DD
A
V
DD
LOOP
_
FI
L
T
ER
CL
KM
O
DE
S
E
L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
S
CL
K
S
DI
O
S
DO
CS
B
IO
_UP
D
A
TE
R
ESET
P
W
RDO
W
N
H
OLD
OV
E
R
EF
SEL
EC
T
S4
S3
A
V
DD
A
VSS
DAC_O
UT
B
DAC_O
UT
A
V
DD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DVDD_I/O
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
S1
S2
AVDD
REFA_IN
REFA_INB
AVDD3
REFB_IN
REFB_INB
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL DIE ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
DAC_RSET
AVDD3
AVDD
AVSS
AVDD
FDBK_IN
FDBK_INB
AVSS
OUT_CMOS
AVDD3
AVDD
OUT
OUTB
AVSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
06744-
002
AD9549
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
1
I
Power
DVDD_I/O
I/O Digital Supply.
2, 4, 6, 8
I
Power
DVSS
Digital Ground. Connect to ground.
3, 5, 7
I
Power
DVDD
Digital Supply.
9, 10, 54, 55
I/O
3.3 V CMOS
S1, S2, S3, S4
Configurable I/O Pins. These pins are configured under program control (see
the Status and Warnings section) and do not have internal pull-up/pull-down
resistors.
11, 19, 23 to
26, 29, 30, 36,
42, 44, 45, 53
I
Power
AVDD
Analog Supply. Connect to a nominal 1.8 V supply.
12
I
Differential
input
REFA_IN
Frequency/Phase Reference A Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
13
I
Differential
input
REFA_INB
Complementary Frequency/Phase Reference A Input. Complementary signal
to the input provided on Pin 12. If using a single-ended, dc-coupled CMOS
signal into REFA_IN, bypass this pin to ground with a 0.01 μF capacitor.
14, 46, 47, 49
I
Power
AVDD3
Analog Supply. Connect to a nominal 3.3 V supply.
15
I
Differential
input
REFB_IN
Frequency/Phase Reference B Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
16
I
Differential
input
REFB_INB
Complementary Frequency/Phase Reference B Input. Complementary signal
to the input provided on Pin 15. If using a single-ended, dc-coupled CMOS
signal into REFB_IN, bypass this pin to ground with a 0.01 μF capacitor.
17, 18
NC
No Connect. These are excess, unused pins that can be left floating.
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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