參數(shù)資料
型號(hào): AD9547BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 100/104頁
文件大小: 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
Data Sheet
AD9547
Rev. E | Page 95 of 104
Table 142. Input Reference Status
Address
Bit
Bit Name
Description
0x0D0C
7
Profile selected
The control logic sets this bit when it assigns Ref A to one of the eight profiles.
[6:4]
Selectedprofile
The index (0 to 7) of the profile assigned to Ref A.
Note that these bits are meaningless unless Bit 7 = 1.
3
Valid
Ref A is valid for use (that is, it is unfaulted, and its validation timer has expired).
2
Fault
Ref A is not valid for use.
1
Fast
IfBit 7 = 1, this bit indicatesthat the frequency ofRefA is higher thanallowedby its profilesettings.
If Bit 7 = 0, this bit indicates that the frequency of Ref A is above the maximum input reference
frequency supported by the device.
0
Slow
IfBit 7 = 1, this bit indicatesthat the frequency ofRefA is lowerthanallowedby itsprofilesettings.
If Bit 7 = 0, this bit indicates that the frequency of Ref A is below the minimum input reference
frequency supported by the device.
0x0D0D
[7:0]
Same as 0x0D0C but for REF AA instead of REF A.
0x0D0E
[7:0]
Same as 0x0D0C but for REF B instead of REF A.
0x0D0F
[7:0]
Same as 0x0D0C but for REF BB instead of REF A.
0x0D10
[7:0]
Unused
Unused.
0x0D11
[7:0]
0x0D12
[7:0]
0x0D13
[7:0]
Table 143. Holdover History1
Address
Bit
Bit Name
Description
0x0D14
[7:0]
Tuningword
history
Tuning word readback, Bits[7:0].
0x0D15
[7:0]
Tuning word readback, Bits[15:8].
0x0D16
[7:0]
Tuning word readack, Bits[23:16].
0x0D17
[7:0]
Tuning word readback, Bits[31:24].
0x0D18
[7:0]
Tuning word readback, Bits[39:32].
0x0D19
[7:0]
Tuning word readback, Bits[47:40].
1
These registers contain the current 48-bit DDS frequency tuning word generated by the tuning word history logic.
NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)
Table 144. Write Protect
Address
Bit
Bit Name
Description
0x0E00
[7:2]
Unused
Unused.
1
Half rate mode
EEPROM serial communicationrate.
0 (default) = 400 kHz (normal).
1 = 200 kHz.
0
Write enable
EEPROM write enable/protect.
0 (default) = EEPROM is write protected.
1 = EEPROM is write enabled.
Table 145. Condition
Address
Bit
Bit Name
Description
0x0E01
[7:5]
Unused
Unused.
[4:0]
Condition value
Whenset to a nonzero value (default = 0), these bits establishthe conditionfor EEPROM downloads.
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