- 您現在的位置：買賣IC網 > PDF目錄16544 > AD9520-5/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9520-5 PDF資料下載
參數資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 62/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁當前第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
Data Sheet
AD9520-5
Rev. A | Page 65 of 76
Table 49. Output Driver Control
Reg
Addr
(Hex) Bits
Name
Description
0x0F0 7
OUT0 format
Selects the output type for OUT0.
0: LVPECL (default).
1: CMOS.
[6:5]
OUT0 CMOS
configuration
Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1.
Bits[6:5]
OUT0A
OUT0B
00
01
10
11 (default)
Tristate
On
Tristate
On
Tristate
On
[4:3]
OUT0 polarity
Sets the output polarity for OUT0.
Bit 7
Bit 4
Bit 3
Output Type
OUT0A
OUT0B
0 (default)
0
1
X
0 (default)
0
1
0 (default)
1
0
1
0
1
LVPECL
CMOS
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting
[2:1]
OUT0 LVPECL
differential voltage
Sets the LVPECL output differential voltage (VOD).
Bit 2
Bit 1
VOD (mV)
0
1 (default)
1
0
1
0 (default)
1
400
600
780
960
0
OUT0 LVPECL
power-down
LVPECL power-down.
0: normal operation (default).
1: safe power-down.
0x0F1 [7:0]
OUT1 control
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
0x0F2 [7:0]
OUT2 control
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
0x0F3 [7:0]
OUT3 control
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
0x0F4 [7:0]
OUT4 control
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
0x0F5 [7:0]
OUT5 control
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
0x0F6 [7:0]
OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0x0F7 [7:0]
OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0x0F8 [7:0]
OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0x0F9 [7:0]
OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0x0FA [7:0]
OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0x0FB [7:0]
OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0x0FC 7
CSDLD en OUT7
OUT7 is enabled only if the CSDLD signal is high.
Bit 7
CSDLD
Signal
OUT7 Enable Status
0
1
0
1
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enables OUT7 if not powered down by other settings. For this feature, use current
source digital lock detect and set the enable LD pin comparator bit (Register 0x01D[3]).
6
CSDLD en OUT6
OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
5
CSDLD en OUT5
OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
4
CSDLD en OUT4
OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
3
CSDLD en OUT3
OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT2
OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT1
OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT0
OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0x0FD [7:4]
Unused
Unused.
3
CSDLD en OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT9
OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT8
OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
相關PDF資料 |
PDF描述 |
|---|---|
| ACM06DRYN | CONN EDGECARD 12POS DIP .156 SLD |
| SPD42R-823M | INDUCTOR PWR SHIELDED 82UH SMD |
| EBA30DTKS | CONN EDGECARD 60POS DIP .125 SLD |
| CDK2000-LCO | KIT EVAL PROTOTYPING CS2300-CP |
| ECE-T2GP821FA | CAP ALUM 820UF 400V 20% SNAP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521KH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
發(fā)布緊急采購，3分鐘左右您將得到回復。