參數(shù)資料
型號： AD9520-1/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 56/80頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9520-1
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9520-1
主要屬性： 12 LVPECL/24 CMOS 輸出時鐘發(fā)生器，帶 2.5 GHz VCO
次要屬性： SPI 和 I2C 兼容控制端口
已供物品： 板，線纜，CD，電源
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9520-1BCPZ-REEL7-ND - IC CLOCK GEN 2.5GHZ VCO 64LFCSP
AD9520-1BCPZ-ND - IC CLOCK GEN 2.5GHZ VCO 64LFCSP
AD9520-1
Data Sheet
Rev. A | Page 6 of 80
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE OFFSET IN ZERO DELAY
REF refers to REFIN (REF1)/REFIN (REF2)
Phase Offset (REF-to-LVPECL Clock Output Pins)
in Internal Zero Delay Mode
560
1060
1310
ps
When N delay and R delay are bypassed
Phase Offset (REF-to-LVPECL Clock Output Pins) in
Internal Zero Delay Mode
320
+50
+240
ps
When N delay setting = 110b, and R delay is bypassed
Phase Offset (REF-to-CLK Input Pins) in External
Zero Delay Mode
140
630
870
ps
When N delay and R delay are bypassed
Phase Offset (REF-to-CLK Input Pins) in External
Zero Delay Mode
460
20
+200
ps
When N delay setting = 011b, and R delay is bypassed
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/ Phase
Frequency Detector2
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the
value of the N divider)
500 kHz PFD Frequency
165
dBc/Hz
1 MHz PFD Frequency
162
dBc/Hz
10 MHz PFD Frequency
152
dBc/Hz
50 MHz PFD Frequency
144
dBc/Hz
PLL Figure of Merit (FOM)
222
dBc/Hz
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is
an approximation of the PFD/CP in-band phase
noise (in the flat region) inside the PLL loop
bandwidth; when running closed-loop, the phase
noise, as observed at the VCO output, is increased
by 20 log(N); PLL figure of merit decreases with
decreasing slew rate; see Figure 12
PLL DIGITAL LOCK DETECT WINDOW3
Signal available at the LD, STATUS, and REFMON
pins when selected by appropriate register settings;
the lock detect threshold varies linearly with the
value of the CPRSET resistor
Lock Threshold (Coincidence of Edges)
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from unlock to lock)
Low Range (ABP 1.3 ns, 2.9 ns)
3.5
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
7.5
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
High Range (ABP 6.0 ns)
3.5
ns
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Unlock Threshold (Hysteresis)3
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from lock to unlock)
Low Range (ABP 1.3 ns, 2.9 ns)
7
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
15
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
High Range (ABP 6.0 ns)
11
ns
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2
In-band means within the LBW of the PLL.
3
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9520-2 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO
AD9520-2/PCBZ 功能描述:BOARD EVAL AD9520-2 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9520-2BCPZ 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-2BCPZ-REEL7 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-3 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO
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