參數資料
型號： AD9520-0/PCBZ
廠商： Analog Devices Inc
文件頁數： 4/80頁
文件大?。?/td> 0K
描述： BOARD EVAL AD9520-0
設計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
已用 IC / 零件： AD9520-0
已供物品： 板
AD9520-0
Data Sheet
Rev. A | Page 12 of 80
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ABSOLUTE TIME JITTER
Application example based on a typical setup
using an external 245.76 MHz VCXO (Toyocom
TCO-2112); reference = 15.36 MHz; R divider = 1
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
54
fs rms
Integration BW = 200 kHz to 5 MHz
77
fs rms
Integration BW = 200 kHz to 10 MHz
109
fs rms
Integration BW = 12 kHz to 20 MHz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
79
fs rms
Integration BW = 200 kHz to 5 MHz
114
fs rms
Integration BW = 200 kHz to 10 MHz
163
fs rms
Integration BW = 12 kHz to 20 MHz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
124
fs rms
Integration BW = 200 kHz to 5 MHz
176
fs rms
Integration BW = 200 kHz to 10 MHz
259
fs rms
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; measured at rising edge of clock signal
CLK = 622.08 MHz
46
fs rms
Integration bandwidth = 12 kHz to 20 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
CLK = 622.08 MHz
64
fs rms
Integration bandwidth = 12 kHz to 20 MHz
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
CLK = 1000 MHz
223
fs rms
Calculated from SNR of ADC method
Any LVPECL Output = 100 MHz
Broadband jitter
Divide Ratio = 10
CLK = 500 MHz
209
fs rms
Calculated from SNR of ADC method
Any LVPECL Output = 100 MHz
Broadband jitter
Divide Ratio = 5
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO
CLK = 200 MHz
325
fs rms
Calculated from SNR of ADC method
Any CMOS Output Pair = 100 MHz
Broadband jitter
Divide Ratio = 2
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
Channel Divider = 2; Duty-Cycle Correction = Off
230
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
215
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
326
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Channel Divider = 8; Duty-Cycle Correction = Off
362
fs rms
Calculated from SNR of ADC method
(broadband jitter)
相關PDF資料
PDF描述
SRR4018-270Y INDUCTOR POWER 27UH 0.77A 4018
MLF2012E8R2K INDUCTOR MULTILAYER 8.2UH 0805
V110B48E150BL CONVERTER MOD DC/DC 48V 150W
AD9515/PCBZ BOARD EVAL CLOCK 2CH AD9515
ECC30DCAN CONN EDGECARD 60POS R/A .100 SLD
相關代理商/技術參數
參數描述
AD9520-1 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO
AD9520-1/PCBZ 功能描述:BOARD EVAL FOR AD9520-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9520-1BCPZ 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-1BCPZ-REEL7 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9520-2 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*