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參數(shù)資料
| 型號： | AD9517-3A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/80頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-3A |
| 設(shè)計資源： | AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-3 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-3A |
| 主要屬性： | 2 輸入，12 輸出，2.0GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9517-3
Data Sheet
Rev. E | Page 64 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01B
7
VCO
Enables or disables VCO frequency monitor.
frequency monitor
0: disables VCO frequency monitor (default).
1: enables VCO frequency monitor.
6
REF2 (REFIN)
Enables or disables REF2 frequency monitor.
frequency monitor
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
5
REF1 (REFIN)
frequency monitor
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
[4:0]
REFMON
Selects the signal that is connected to the REFMON pin.
pin control
4
3
2
1
0
Level or
Dynamic
Signal
Signal at REFMON Pin
0
LVL
Ground (dc) (default).
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
1
0
DYN
REF2 clock (not available in differential mode).
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
0
1
LVL
Status REF1 frequency (active high).
0
1
0
LVL
Status REF2 frequency (active high).
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
LVL
Status of VCO frequency (active high).
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
0
1
LVL
Digital lock detect (DLD); active low.
0
1
0
LVL
Holdover active (active high).
0
1
LVL
LD pin comparator output (active high).
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency (active low).
1
0
LVL
Status of REF2 frequency (active low).
1
0
1
LVL
(Status of REF1 frequency) AND (Status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (Status of VCO).
1
0
1
LVL
Status of VCO frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
Digital lock detect (DLD); active low.
1
0
LVL
Holdover active (active low).
1
LVL
LD pin comparator output (active low).
0x01C
7
Disable
Disables or enables the switchover deglitch circuit.
switchover
0: enables switchover deglitch circuit (default).
deglitch
1: disables switchover deglitch circuit.
6
Select REF2
If Register 0x01C, Bit 5 = 0b, selects reference for PLL.
0: selects REF1 (default).
1: selects REF2.
5
Use REF_SEL pin
Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
[4:3]
Reserved
Reserved (default: 00b).
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