參數(shù)資料
型號(hào)： AD9517-3A/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/80頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9517-3A
設(shè)計(jì)資源： AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-3 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9517-3A
主要屬性： 2 輸入，12 輸出，2.0GHz VCO
次要屬性： CMOS，LVPECL 和 LVDS 兼容
已供物品： 板
Data Sheet
AD9517-3
Rev. E | Page 13 of 80
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DELAY BLOCK ADDITIVE TIME JITTER1
Incremental additive jitter
100 MHz Output
Delay (1600 A, 0x1C) Fine Adj. 000000b
0.54
ps rms
Delay (1600 A, 0x1C) Fine Adj. 101111b
0.60
ps rms
Delay (800 A, 0x1C) Fine Adj. 000000b
0.65
ps rms
Delay (800 A, 0x1C) Fine Adj. 101111b
0.85
ps rms
Delay (800 A, 0x4C) Fine Adj. 000000b
0.79
ps rms
Delay (800 A, 0x4C) Fine Adj. 101111b
1.2
ps rms
Delay (400 A, 0x4C) Fine Adj. 000000b
1.2
ps rms
Delay (400 A, 0x4C) Fine Adj. 101111b
2.0
ps rms
Delay (200 A, 0x1C) Fine Adj. 000000b
1.3
ps rms
Delay (200 A, 0x1C) Fine Adj. 101111b
2.5
ps rms
Delay (200 A, 0x4C) Fine Adj. 000000b
1.9
ps rms
Delay (200 A, 0x4C) Fine Adj. 101111b
3.8
ps rms
1
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 30 k pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
3
A
Input Logic 0 Current
110
A
Input Capacitance
2
pF
SCLK (INPUT)
SCLK has an internal 30 k pull-down resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
110
A
Input Logic 0 Current
1
A
Input Capacitance
2
pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
10
nA
Input Logic 0 Current
20
nA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
16
ns
Pulse Width Low, tLOW
16
ns
SDIO to SCLK Setup, tDS
2
ns
SCLK to SDIO Hold, tDH
1.1
ns
SCLK to Valid SDIO and SDO, tDV
8
ns
CS to SCLK Setup and Hold, tS, tH
2
ns
CS Minimum Pulse Width High, tPWH
3
ns
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