參數(shù)資料
型號： AD9516-4/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 61/80頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9516-4 1.8GHZ
產(chǎn)品培訓模塊： Active Filter Design Tools
設計資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-4 BOM
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-4
主要屬性： 2 輸入，14 輸出，1.6GHz VCO
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，CD，電源
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
相關產(chǎn)品： AD9516-4BCPZ-REEL7-ND - IC CLOCK GEN 1.8GHZ VCO 64-LFCSP
AD9516-4BCPZ-ND - IC CLOCK GEN 1.6GHZ VCO 64-LFCSP
AD9516-4
Data Sheet
Rev. C | Page 64 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01B
[4:0]
REFMON
Selects the signal that is connected to the REFMON pin.
pin control
4
3
2
1
0
Level or
Dynamic
Signal
Signal at REFMON Pin
0
LVL
Ground (dc) (default).
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
1
0
DYN
REF2 clock (not available in differential mode).
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
0
1
LVL
Status REF1 frequency (active high).
0
1
0
LVL
Status REF2 frequency (active high).
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
LVL
Status of VCO frequency (active high).
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
0
1
LVL
Digital lock detect (DLD); active low.
0
1
0
LVL
Holdover active (active high).
0
1
LVL
LD pin comparator output (active high).
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency (active low).
1
0
LVL
Status of REF2 frequency (active low).
1
0
1
LVL
(Status of REF1 frequency) AND (Status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (Status of VCO).
1
0
1
LVL
Status of VCO frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
Digital lock detect (DLD); active low.
1
0
LVL
Holdover active (active low).
1
LVL
LD pin comparator output (active low).
0x01C
7
Disable
Disables or enables the switchover deglitch circuit.
switchover
0: enables switchover deglitch circuit (default).
deglitch
1: disables switchover deglitch circuit.
6
Select REF2
If Register 0x01C, Bit 5 = 0, select reference for PLL.
0: selects REF1 (default).
1: selects REF2.
5
Use REF_SEL pin
Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
4
Reserved
0: (default).
3
Reserved
0: (default).
2
REF2 power-on
This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
1
REF1 power-on
This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
0
Differential
reference
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
switchover or REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
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