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參數(shù)資料
| 型號： | AD9516-4/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9516-4 1.8GHZ |
| 產(chǎn)品培訓模塊： | Active Filter Design Tools |
| 設計資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-4 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-4 |
| 主要屬性： | 2 輸入，14 輸出，1.6GHz VCO |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關產(chǎn)品： | AD9516-4BCPZ-REEL7-ND - IC CLOCK GEN 1.8GHZ VCO 64-LFCSP AD9516-4BCPZ-ND - IC CLOCK GEN 1.6GHZ VCO 64-LFCSP |
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AD9516-4
Data Sheet
Rev. C | Page 32 of 80
Phase-Locked Loop (PLL)
CLK
CHARGE PUMP
R DIVIDER
CP
VCP
VSGND
STATUS
CPRSET
DIST
REF
RSET
DIVIDE BY
2, 3, 4, 5, OR 6
A/B
COUNTERS
LD
N DIVIDER
REFMON
LF
BYPASS
LOW DROPOUT
REGULATOR (LDO)
0
1
0
1
VCO
P, P + 1
PRESCALER
REF2
REF1
REFERENCE
SWITCHOVER
HOLD
VCO STATUS
REF_SEL
LOCK
DETECT
STATUS
CLK
PHASE
FREQUENCY
DETECTOR
PROGRAMMABLE
N DELAY
PROGRAMMABLE
R DELAY
PLL
REF
REFIN (REF1)
REFIN (REF2)
06
42
3-
0
64
Figure 46. PLL Functional Blocks
The AD9516 includes an on-chip PLL with an on-chip VCO.
The PLL blocks can be used either with the on-chip VCO to
create a complete phase-locked loop, or with an external VCO
or VCXO. The PLL requires an external loop filter, which
usually consists of a small number of capacitors and resistors.
The configuration and components of the loop filter help to
establish the loop bandwidth and stability of the operating PLL.
The AD9516 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be exploited to
clean up jitter and phase noise on a noisy reference. The exact
choices of PLL parameters and loop dynamics are very application
specific. The flexibility and depth of the AD9516 PLL allow the
part to be tailored to function in many different applications
and signal environments.
Configuration of the PLL
The AD9516 allows flexible configuration of the PLL,
accommodating various reference frequencies, PFD comparison
frequencies, VCO frequencies, internal or external VCO/VCXO,
and loop dynamics. This is accomplished by the various settings
that include the R divider, the N divider, the PFD polarity (only
applicable to external VCO/VCXO), the antibacklash pulse
width, the charge pump current, the selection of internal VCO
or external VCO/VCXO, and the loop bandwidth.
These are managed through programmable register settings (see
Table 52 and Table 54) and by the design of the external loop
filter. Successful PLL operation and satisfactory PLL loop
performance are highly dependent upon proper configuration of
the PLL settings. The design of the external loop filter is crucial
to the proper operation of the PLL. A thorough knowledge of
PLL theory and design is helpful.
ADIsimCLK (V1.2 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9516, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD
transfer function and minimizes phase noise and reference
spurs. The antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD, which in turn determines the correct
antibacklash pulse setting. The antibacklash pulse setting is
specified in the phase/frequency detector parameter of Table 2.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9516-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator |
| AD9516-5/PCBZ | 功能描述:BOARD EVAL FOR AD9516-5 2.5GHZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9516-5BCPZ | 功能描述:IC CLOCK GEN W/PLL 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN W/PLL 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-5PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator |
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