參數(shù)資料
型號: AD9516-3/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 59/80頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9516-3 2.0GHZ
產(chǎn)品培訓(xùn)模塊: Active Filter Design Tools
設(shè)計資源: AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-3 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9516-3
主要屬性: 2 輸入,14 輸出,2GHz VCO
次要屬性: CMOS、LVDS、LVPECL 輸出邏輯,ADIsimCLK&trade 圖形用戶界面
已供物品: 板,線纜,CD,電源
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9516-3BCPZ-ND - IC CLOCK PLL/VCO 2GHZ 64LFCSP
AD9516-3BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2GHZ 64LFCSP
AD9516-3
Data Sheet
Rev. C | Page 62 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x017
[1:0]
Antibacklash
1
0
Antibacklash Pulse Width (ns)
pulse width
0
2.9 (default).
0
1
1.3.
1
0
6.0.
1
2.9.
0x018
[6:5]
Lock detect
counter
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
5 (default).
0
1
16.
1
0
64.
1
255.
4
Digital lock detect
window
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
3
Disable digital
Digital lock detect operation.
lock detect
0: normal lock detect operation (default).
1: disables lock detect.
[2:1]
VCO cal
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
divider
2
1
VCO Calibration Clock Divider
0
2.
0
1
4.
1
0
8.
1
16 (default).
[0]
VCO cal now
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not
zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit
(Register 0x232, Bit 0).
0x019
[7:6]
R, A, B counters
7
6
Action
SYNC pin reset
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Does nothing on SYNC.
[5:3]
R path delay
R path delay (default = 0x00) (see Table 2).
[2:0]
N path delay
N path delay (default = 0x00) (see Table 2).
0x01A
[6]
Reference
frequency monitor
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO Frequency Status Monitor parameter).
threshold
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
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