參數(shù)資料
型號： AD9516-3/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 39/80頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9516-3 2.0GHZ
產品培訓模塊： Active Filter Design Tools
設計資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-3 BOM
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-3
主要屬性： 2 輸入，14 輸出，2GHz VCO
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，CD，電源
產品目錄頁面： 776 (CN2011-ZH PDF)
相關產品： AD9516-3BCPZ-ND - IC CLOCK PLL/VCO 2GHZ 64LFCSP
AD9516-3BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2GHZ 64LFCSP
AD9516-3
Data Sheet
Rev. C | Page 44 of 80
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the
however, with these channel dividers, the number of possible
configurations is even more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
An even DX.Y must be set as MX.Y = NX.Y (low cycles = high
cycles).
An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of
low cycles must be one greater than the number of high
cycles).
If only one divider is bypassed, it must be the second
divider, X.2.
If only one divider has an even divide by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Table 40 through Table 44.
Table 40. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
DX.1
DX.2
Output Duty
Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Even
1
50%
Odd = 3
1
33.3%
Odd = 5
1
40%
Even
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Odd
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Even
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 41. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
Duty Cycle
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
50%
1
50%
X%
1
X%
50%
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
X%
Even, odd
1
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
50%
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
X%
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 42. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
Divider
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Even
1
50%
Odd
1
50%
Even
Even (NX.1 = MX.1)
1
50%
Odd
Even (NX.1 = MX.1)
1
50%
Even
Odd (MX.1 = NX.1 + 1)
1
50%
Odd
Odd (MX.1 = NX.1 + 1)
1
50%
Even
Even (NX.1 = MX.1)
Even (NX.2 = MX.2)
50%
Odd
Even (NX.1 = MX.1)
Even (NX.2 = MX.2)
50%
Even
Odd (MX.1 = NX.1 + 1)
Even (NX.2 = MX.2)
50%
Odd
Odd (MX.1 = NX.1 + 1)
Even (NX.2 = MX.2)
50%
Even
Odd (MX.1 = NX.1 + 1)
Odd (MX.2 = NX.2 + 1)
50%
Odd
Odd (MX.1 = NX.1 + 1)
Odd (MX.2 = NX.2 + 1)
50%
Table 43. Divider 3, Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
DX.1
DX.2
Output
Duty Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Even
1
50%
Odd = 3
1
(1 + X%)/3
Odd = 5
1
(2 + X%)/5
Even
(NX.1 = MX.1)
1
50%
Odd
Even
(NX.1 = MX.1)
1
50%
Even
Odd
(MX.1 = NX.1 + 1)
1
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
1
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
Odd = 5
Odd
(MX.1 = NX.1 + 1)
1
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Odd
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
Odd = 5
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(10NX.1NX.2+ 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
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