參數(shù)資料
型號(hào)： AD9516-1/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 72/80頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD9516-1
產(chǎn)品培訓(xùn)模塊： Active Filter Design Tools
設(shè)計(jì)資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-1 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-1
主要屬性： 2 輸入，14 輸出，2.5GHz VCO
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，電源
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9516-1BCPZ-REEL7-ND - IC CLOCK GEN 2.5GHZ VCO 64-LFCSP
AD9516-1BCPZ-ND - IC CLOCK GEN 2.5GHZ VCO 64-LFCSP
AD9516-1
Data Sheet
Rev. C | Page 74 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x194
4
Divider 1 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 1 phase offset
Phase offset (default = 0x0).
0x195
1
Divider 1 direct to output
Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Divider 1 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x196
[7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x197
7
Divider 2 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6
Divider 2 nosync
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 2 force high
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
4
Divider 2 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 2 phase offset
Phase offset (default = 0x0).
0x198
1
Divider 2 direct to output
Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Divider 2 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x199
[7:4]
Low Cycles Divider 3.1
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 3.1
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high. A value of
0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x19A
[7:4]
Phase Offset Divider 3.2
Refer to LVDS/CMOS channel divider function description (default = 0x0).
[3:0]
Phase Offset Divider 3.1
Refer to LVDS/CMOS channel divider function description (default = 0x0).
0x19B
[7:4]
Low Cycles Divider 3.2
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 3.2
Number of clock cycles (minus 1)of 3.2 divider input during which 3.2 output stays high. A value
of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
相關(guān)PDF資料
PDF描述
MAX876AESA+T IC VREF SERIES PREC 10V 8-SOIC
35PX22MEFC5X11 CAP ALUM 22UF 35V 20% RADIAL
GCC07DRYS-S734 CONN EDGECARD 14POS DIP .100 SLD
MAX6177BASA+ IC VREF SERIES PREC 3.3V 8-SOIC
AD9516-4/PCBZ BOARD EVAL FOR AD9516-4 1.8GHZ
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9516-1XCPZ 制造商:Analog Devices 功能描述:14-CHANNEL CLOCK GENERATOR WITH INTEGRATED 2.8 GHZ VCO - Bulk
AD9516-2 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.2 GHz VCO
AD9516-2/PCBZ 功能描述:BOARD EVAL FOR AD9516-2 2.2GHZ RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9516-2BCPZ 功能描述:IC CLOCK PLL/VCO 2.2GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9516-2BCPZ-REEL7 功能描述:IC CLOCK PLL/VCO 2.2GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*