參數資料
型號: AD9516-1/PCBZ
廠商: Analog Devices Inc
文件頁數: 60/80頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9516-1
產品培訓模塊: Active Filter Design Tools
設計資源: AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-1 BOM
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9516-1
主要屬性: 2 輸入,14 輸出,2.5GHz VCO
次要屬性: CMOS、LVDS、LVPECL 輸出邏輯,ADIsimCLK&trade 圖形用戶界面
已供物品: 板,線纜,電源
產品目錄頁面: 776 (CN2011-ZH PDF)
相關產品: AD9516-1BCPZ-REEL7-ND - IC CLOCK GEN 2.5GHZ VCO 64-LFCSP
AD9516-1BCPZ-ND - IC CLOCK GEN 2.5GHZ VCO 64-LFCSP
Data Sheet
AD9516-1
Rev. C | Page 63 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01A
[5:0]
LD pin control
Selects the signal that is connected to the LD pin.
5
4
3
2
1
0
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock, low = unlock) (default).
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
1
HIZ
High-Z LD pin.
0
1
0
CUR
Current source lock detect (110 A when DLD is true).
0
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when indifferential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active
high.
1
0
1
LVL
Status REF1 frequency (active high).
1
0
1
0
LVL
Status REF2 frequency (active high).
1
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency (active high).
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
0
LVL
Holdover active (active high).
1
0
1
LVL
Not available. Do not use.
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active
low.
1
0
1
LVL
Status of REF1 frequency (active low).
1
0
LVL
Status of REF2 frequency (active low).
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
Digital lock detect (DLD); active low.
1
0
LVL
Holdover active (active low).
1
LVL
Not available. Do not use.
0x01B
7
VCO frequency
Enables or disables VCO frequency monitor.
monitor
0: disables VCO frequency monitor (default).
1: enables VCO frequency monitor.
6
REF2 (REFIN)
Enables or disables REF2 frequency monitor.
frequency monitor
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
5
REF1 (REFIN)
frequency monitor
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
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