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參數(shù)資料
| 型號(hào)： | AD9515BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 2OUT PLL 32LFCSP |
| 設(shè)計(jì)資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 無 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9515/PCBZ-ND - BOARD EVAL CLOCK 2CH AD9515 |
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Data Sheet
AD9515
Rev. A | Page 25 of 28
APPLICATIONS
USING THE AD9515 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity require-
ments scale with the analog input frequency and resolution,
with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite resolution
where the step size and quantization error can be ignored, the
available SNR can be expressed approximately by
×
=
J
ft
SNR
2π
1
log
20
where f is the highest analog frequency being digitized.
tj is the rms jitter on the sampling clock.
Figure 35 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
SNR
(dB)
ENOB
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
T
J = 100
f
S
200
f
S
400
f
S
1ps
2ps
10ps
SNR = 20log
1
2
πf
ATJ
05597-091
Figure 35. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9515 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9515 provide the lowest jitter clock signals
available from the AD9515. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 31 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 36. The resistor network is
designed to match the transmission line impedance (50 ) and
the switching threshold (VS 1.3 V).
VS
LVPECL
50
50
SINGLE-ENDED
(NOT COUPLED)
VS
LVPECL
127
127
83
83
VT = VS – 1.3V
05597-030
Figure 36. LVPECL Far-End Termination
VS
LVPECL
100
DIFFERENTIAL
(COUPLED)
VS
LVPECL
100
0.1nF
200
200
05597-031
Figure 37. LVPECL with Parallel Transmission Line
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9516-0BCPZ | IC CLOCK GEN 2.8GHZ VCO 64-LFCSP |
| AD9516-1BCPZ-REEL7 | IC CLOCK GEN 2.5GHZ VCO 64-LFCSP |
| AD9516-2BCPZ | IC CLOCK PLL/VCO 2.2GHZ 64LFCSP |
| AD9516-3BCPZ-REEL7 | IC CLOCK PLL/VCO 2GHZ 64LFCSP |
| AD9516-4BCPZ-REEL7 | IC CLOCK GEN 1.8GHZ VCO 64-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD95160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Channel Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0/PCBZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 64-LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9516-0_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0BCPZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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