參數(shù)資料
型號(hào): AD9515BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 13/28頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK DIST 2OUT PLL 32LFCSP
設(shè)計(jì)資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標(biāo)準(zhǔn)包裝: 1,500
類型: 扇出緩沖器(分配),除法器
PLL: 無(wú)
輸入: 時(shí)鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.6GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
配用: AD9515/PCBZ-ND - BOARD EVAL CLOCK 2CH AD9515
AD9515
Data Sheet
Rev. A | Page 20 of 28
PROGRAMMING
Table 10. S0—OUT1 Delay Full Scale
S0
Delay
0
Bypassed
1/3
1.5 ns
2/3
5 ns
1
10 ns
Table 11. S1—Output Logic Configuration
S1
OUT0
OUT1
0
LVPECL 790 mV
LVDS
1/3
LVPECL 400 mV
LVDS
2/3
LVPECL 790 mV
CMOS
1
LVPECL 400 mV
CMOS
Table 12. S2, S3, and S4—OUT0
S2
S3
S4
OUT0
Divide (Duty Cycle1)
OUT0
Phase
0
1
0
1/3
0
2 (50%)
0
2/3
0
3 (33%)
0
1
0
4 (50%)
0
1/3
0
5 (40%)
0
1/3
0
6 (50%)
0
2/3
1/3
0
7 (43%)
0
1
1/3
0
8 (50%)
0
2/3
0
9 (44%)
0
1/3
2/3
0
10 (50%)
0
2/3
0
11 (45%)
0
1
2/3
0
12 (50%)
0
1
0
OUT0 OFF
1/3
1
0
14 (50%)
0
2/3
1
0
15 (47%)
0
1
0
16 (50%)
0
1/3
17 (47%)
0
1/3
0
1/3
18 (50%)
0
2/3
0
1/3
19 (47%)
0
1
0
1/3
20 (50%)
0
1/3
21 (48%)
0
1/3
22 (50%)
0
2/3
1/3
23 (48%)
0
1
1/3
24 (50%)
0
2/3
1/3
25 (48%)
0
S2
S3
S4
OUT0
Divide (Duty Cycle1)
OUT0
Phase
1/3
2/3
1/3
26 (50%)
0
2/3
1/3
27 (48%)
0
1
2/3
1/3
28 (50%)
0
1
1/3
29 (48%)
0
1/3
1
1/3
30 (50%)
0
2/3
1
1/3
31 (48%)
0
1
1/3
32 (50%)
0
2/3
2 (50%)
1
1/3
0
2/3
4 (50%)
1
2/3
0
2/3
4 (50%)
2
1
0
2/3
4 (50%)
3
0
1/3
2/3
8 (50%)
1
1/3
2/3
8 (50%)
2
2/3
1/3
2/3
8 (50%)
3
1
1/3
2/3
8 (50%)
4
0
2/3
8 (50%)
5
1/3
2/3
8 (50%)
6
2/3
8 (50%)
7
1
2/3
16 (50%)
1
0
1
2/3
16 (50%)
2
1/3
1
2/3
16 (50%)
3
2/3
1
2/3
16 (50%)
4
1
2/3
16 (50%)
5
0
1
16 (50%)
6
1/3
0
1
16 (50%)
7
2/3
0
1
16 (50%)
8
1
0
1
16 (50%)
9
0
1/3
1
16 (50%)
10
1/3
1
16 (50%)
11
2/3
1/3
1
16 (50%)
12
1
1/3
1
16 (50%)
13
0
2/3
1
16 (50%)
14
1/3
2/3
1
16 (50%)
15
2/3
1
32 (50%)
1
2/3
1
32 (50%)
2
0
1
32 (50%)
3
1/3
1
32 (50%)
4
2/3
1
32 (50%)
5
1
Do not use
1 Duty cycle is the clock signal high time divided by the total period.
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