- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1893 > AD9398KSTZ-150 (Analog Devices Inc)IC INTERFACE 150MHZ HDMI 100LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9398KSTZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/44頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 150MHZ HDMI 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9398
Rev. 0 | Page 12 of 44
AUDIO PLL SETUP
Data contained in the audio infoframes, among other registers,
define for the AD9398 HDMI receiver not only the type of
audio, but the sampling frequency (fS). The audio infoframe also
contains information about the N and CTS values used to
recreate the clock. With this information, it is possible to
regenerate the audio sampling frequency. The audio clock is
regenerated by dividing the 20-bit CTS value into the TMDS
clock, then multiplying by the 20-bit N value. This yields a
multiple of the sampling frequency of either 128 × fS or 256 × fS.
It is possible for this to be specified up to 1024 × fS.
05678-007
SINK DEVICE
SOURCE DEVICE
1N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
128 × fS
N
VIDEO
CLOCK
128 × fS
TMDS
CLOCK
N1
CTS1
DIVIDE
BY
N
CYCLE
TIME
COUNTER
REGISTER
N
DIVIDE
BY
CTS
MULTIPLY
BY
N
Figure 7. N and CTS for Audio Clock
In order to provide the most flexibility in configuring the audio
sampling clock, an additional PLL is employed. The PLL
characteristics are determined by the loop filter design, the PLL
charge pump current, and the VCO range setting. The loop
filter design is shown in Figure 8.
CP
8nF
CZ
80nF
RZ
1.5k
Ω
FILT
PVD
05678-010
Figure 8. PLL Loop Filter Detail
To fully support all audio modes for all video resolutions up
to 1080p, it is necessary to adjust certain audio-related
registers from their power-on default values. Table 9
describes these registers and gives the recommended
settings.
Table 9. AD9398 Audio Register Settings
Register
Bits
Recommended
Setting
Function
Comments
0x01
7:0
0x00
PLL Divisor (MSBs)
0x02
7:4
0x40
PLL Divisor (LSBs)
7:6
01
VCO Range
5:3
010
Charge Pump Current
The analog video PLL is also used for the audio clock circuit when in
HDMI mode. This is done automatically.
0x03
2
1
PLL Enable
In HDMI mode, this bit enables a lower frequency to be used for
audio MCLK generation.
0x34
4
0
Audio Frequency Mode
Override
Allows the chip to determine the low frequency mode of the audio
PLL.
7
1
PLL Enable
This enables the analog PLL to be used for audio MCLK generation.
6:4
011
MCLK PLL Divisor
When the analog PLL is enabled for MCLK generation, another
frequency divider is provided. These bits set the divisor to 4.
3
0
N/CTS Disable
The N and CTS values should always be enabled.
0x58
2:0
0**
MCLK Sampling Frequency
000 = 128 × fS
001 = 256 × fS
010 = 384 × fS
011 = 512 × fS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9708ARU | IC DAC 8BIT 100MSPS 28-TSSOP |
| AD974BN | IC DAS 16BIT 4CH 200KSPS 28-DIP |
| AD9755ASTZRL | IC DAC 14BIT 300MSPS 48-LQFP |
| AD9762ARU | IC DAC 12BIT 125MSPS 28-TSSOP |
| AD9764AR | IC DAC 14BIT 125MSPS 28-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9410 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 210 MSPS A/D Converter |
| AD9410/PCB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR AD9410 - Bulk |
| AD9410BSQ | 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 10-bit Parallel 80-Pin LQFP EP 制造商:Analog Devices 功能描述:ADC SGL FLASH 210MSPS 10-BIT PARALLEL 80LQFP EP - Trays 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD9410BSQZ | 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 10-bit Parallel 80-Pin LQFP EP 制造商:Analog Devices 功能描述:ADC SGL FLASH 210MSPS 10-BIT PARALLEL 80LQFP EP - Trays |
| AD9410BSVZ | 功能描述:IC ADC 10BIT 210MSPS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。