VDD = V
參數(shù)資料
型號(hào)： AD9393BBCZRL-80
廠商： Analog Devices Inc
文件頁數(shù)： 34/40頁
文件大?。?/td> 0K
描述： IC INTERFACE 80MHZ HDMI 76CSPBGA
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： HDMI，DVI，接收器
接口： 模擬，DVI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 76-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 76-CSPBGA（6x6）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
AD9393
Rev. 0 | Page 4 of 40
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, unless otherwise noted.
Table 2.
Parameter
Test
Level
Conditions
Min
Typ
Max
Unit
DC DIGITAL I/O Specifications
High-Level Input Voltage (VIH)
VI
2.5
V
Low-Level Input Voltage (VIL)
VI
0.8
V
High-Level Output Voltage (VOH)
VI
VDD 0.1
V
Low-Level Output Voltage (VOL)
VI
VDD 0.1
0.1
V
DC SPECIFICATIONS
Output High Level
IV
Output drive = high strength
36
mA
IOHD (VOUT = VOH)
IV
Output drive = low strength
24
mA
Output Low Level
IV
Output drive = high strength
12
mA
IOLD (VOUT = VOL)
IV
Output drive = low strength
8
mA
DCLK High Level
IV
Output drive = high strength
40
mA
VOHC (VOUT = VOH)
IV
Output drive = low strength
20
mA
DCLK Low Level
IV
Output drive = high strength
30
mA
VOLC (VOUT = VOL)
IV
Output drive = low
15
mA
Differential Input Voltage, Single-Ended Amplitude
IV
75
700
mV
POWER SUPPLY
VD
IV
3.15
3.3
3.47
V
VDD
IV
1.7
3.3
347
V
DVDD
IV
1.7
1.8
1.9
V
PVDD
IV
1.7
1.8
1.9
V
Power—54 MHz, YCrCb 422, CSC Disabled
485
mW
Supply Current (Worst Pattern)1
IVD
V
95
mA
IVDD
V
18
mA
V
51
mA
IPVDD
V
26
mA
Power—74.25 MHz, RGB, CSC Disabled
593
mW
Supply Current (Worst Pattern)1
IVD
V
109
mA
IVDD
V
38
mA
IDVDD
V
66
mA
IPVDD
V
26
mA
Power-Down Power
VI
130
mW
AC SPECIFICATIONS
Intrapair (+ to ) Differential Input Skew (tDPS)
IV
0.4
tBIT
Channel-to-Channel Differential Input Skew (tCCS)
IV
0.6
tPIXEL
Low-to-High Transition Time for Data and Controls (DLHT)
IV
Output drive = high; CL = 10 pF
1000
ps
IV
Output drive = low; CL = 5 pF
ps
Low-to-High Transition Time for DCLK (DLHT)
IV
Output drive = high; CL = 10 pF
1000
ps
IV
Output drive = low; CL = 5 pF
ps
High-to-Low Transition Time for Data and Controls (DHLT)
IV
Output drive = high; CL = 10 pF
1000
ps
IV
Output drive = low; CL = 5 pF
ps
High-to-Low Transition Time for DCLK (DHLT)
IV
Output drive = high; CL = 10 pF
1000
ps
IV
Output drive = low; CL = 5 pF
ps
Clock-to-Data Skew3 (tSKEW)
IV
0.5
+2.0
ns
Duty Cycle, DCLK3
IV
45
50
%
DCLK Frequency (fCIP)
VI
20
80
MHz
1 Worst-case pattern is alternating black and white pixels.
2 DCLK load = 10 pF, data load = 5 pF.
3 Drive strength = high.
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