參數(shù)資料
型號(hào)： AD9393BBCZRL-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/40頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 80MHZ HDMI 76CSPBGA
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： HDMI，DVI，接收器
接口： 模擬，DVI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 76-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 76-CSPBGA（6x6）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
AD9393
Rev. 0 | Page 10 of 40
One of the three input channels is represented in Figure 4.
In each processing channel, the three inputs are multiplied
by three separate coefficients marked a1, a2, and a3. These
coefficients are divided by 4096 to obtain nominal values
ranging from 0.9998 to +0.9998. The variable labeled a4 is
used as an offset control. The CSC_MODE setting is the same
for all three processing channels. This multiplies all coefficients
and offsets by a factor of 2CSC_MODE.
The functional diagram for a single channel of the CSC (as
shown in Figure 4) is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3,
b4, c1, c2, c3, and c4.
×2
2
1
0
a1[12:0]
a2[12:0]
a3[12:0]
RIN[11:0]
GIN[11:0]
BIN[11:0]
+
×4
CSC_MODE[1:0]
a4[12:0]
ROUT[11:0]
+
1
4096
×
1
4096
1
4096
+
×
0
8043-
00
6
Figure 4. Single CSC Channel
A programming example and register settings for several
common conversions are listed in the Color Space Converter
For a detailed functional description and more programming
examples that are compatible with the AD9393, refer to the
AN-795 Application Note, AD9880 Color Space Converter
User's Guide.
AUDIO PLL SETUP
Data contained in the audio infoframes (among other registers)
defines for the AD9393 HDMI receiver not only the type of
audio, but also the sampling frequency (fS). The audio info-
frame also contains information about the N and CTS values
used to recreate the clock. With this information, it is possible
to regenerate the audio sampling frequency. The audio clock is
regenerated by dividing the 20-bit CTS value into the TMDS
clock, then multiplying by the 20-bit N value. This yields a
multiple of the sampling frequency of either 128 × fS or 256 ×
fS. It is possible for this to be specified up to 1024 × fS.
SINK DEVICE
SOURCE DEVICE
*N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
128 ×
fS
N
VIDEO
CLOCK
128 ×
fS
TMDS
CLOCK
N*
CTS*
DIVIDE
BY
N
CYCLE
TIME
COUNTER
REGISTER
N
÷ CTS
× N
08
04
3-
0
07
Figure 5. N and CTS for Audio Clock
To provide the most flexibility in configuring the audio
sampling clock, an additional PLL is employed. The PLL
characteristics are determined by the loop filter design (see
Figure 6), the PLL charge pump current, and the VCO range
setting.
CP
8nF
CZ
80nF
RZ
1.5k
FILT
PVDD
0
80
43
-0
08
Figure 6. PLL Loop Filter Detail
To fully support all audio modes for all video resolutions up
to 1080i, it is necessary to adjust certain audio-related registers
from their power-on default values. Table 7 describes these
registers and gives the recommended settings.
Table 7. Audio Register Settings
Register
Bits
Recommended
Setting
Function
Comments
0x01
[7:0]
0x00
PLL divisor (MSBs)
The video PLL is used for the audio clock circuit when in HDMI mode. This
is done automatically.
0x02
[7:4]
0x40
PLL divisor (LSBs)
0x03
[7:6]
01
VCO range
[5:3]
010
Charge pump current
[2]
1
PLL enable
In HDMI mode, this bit enables a lower frequency to be used for audio
MCLK generation.
0x34
[5:4]
11
Audio frequency mode
override
Allows the chip to determine the low frequency mode of the audio PLL.
0x58
[7]
1
MCLK PLL enable
This enables the analog PLL to be used for audio MCLK generation.
[6:4]
001
MCLK PLL divisor
When the analog PLL is enabled for MCLK generation, another frequency
divider is provided; these bits set the divisor to 2.
[3]
0
N/CTS disable
The N and CTS values should always be enabled.
[2:0]
0**
MCLK sampling
frequency
000 = 128 × fS
001 = 256 × fS
010 = 384 × fS
011 = 512 × fS
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