參數(shù)資料
型號： AD9393BBCZRL-80
廠商： Analog Devices Inc
文件頁數(shù)： 13/40頁
文件大?。?/td> 0K
描述： IC INTERFACE 80MHZ HDMI 76CSPBGA
標(biāo)準(zhǔn)包裝： 2,500
應(yīng)用： HDMI，DVI，接收器
接口： 模擬，DVI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 76-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 76-CSPBGA（6x6）
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
AD9393
Rev. 0 | Page 20 of 40
Hex Address
Read/Write
Bits
Default
Value
Register Name
Description
0xBD
Read
[4]
0
Field repeat
FR—new field or repeated field.
0 = new field or picture.
1 = repeated field.
[1:0]
0
MPEG frame
MF[1:0]. This identifies whether frame is an I, B, or P picture.
00 = unknown.
01 = I picture.
10 = B picture.
11 = P picture.
0xBE
Read
[7:0]
0
Reserved.
0xBF
Read
[6:0]
0
New data flags
New data flags (see Register 0x87).
0xC0
Read
[7:0]
0
Audio content protection
packet (ACP) type
Audio content protection packet (ACP) type.
0x00 = generic audio.
0x01 = IEC60958-identified audio.
0x02 = DVD audio.
0x03 = reserved for super audio CD (SACD).
0x04 to 0xFF = reserved.
0xC1
Read
[7:0]
0
ACP Packet Byte 0
ACP Packet Byte 0 (ACP_PB0).
0xC2
Read
[7:0]
0
ACP_PB1
ACP_PB1.
0xC3
Read
[7:0]
0
ACP_PB2
ACP_PB2.
0xC4
Read
[7:0]
0
ACP_PB3
ACP_PB3.
0xC5
Read
[7:0]
0
ACP_PB4
ACP_PB4.
0xC6
Read
[7:0]
0
ACP_PB5
ACP_PB5.
0xC7
Read
[6:0]
0
New data flags
New data flags (see Register 0x87).
0xC8
Read
[7]
0
ISRC1 continued
International standard recording code (ISRC1) continued.
This indicates an ISRC2 packet is being transmitted.
[6]
0
ISRC1 valid
0 = ISRC1 status bits and PBs not valid.
1 = ISRC1 status bits and PBs valid.
[2:0]
0
ISRC1 status
001 = starting position.
010 = intermediate position.
100 = final position.
0xC9
Read
[7:0]
0
ISRC1 Packet Byte 0
ISRC1 Packet Byte 0 (ISRC1_PB0).
0xCA
Read
[7:0]
0
ISRC1_PB1
ISRC1_PB1.
0xCB
Read
[7:0]
0
ISRC1_PB2
ISRC1_PB2.
0xCC
Read
[7:0]
0
ISRC1_PB3
ISRC1_PB3.
0xCD
Read
[7:0]
0
ISRC1_PB4
ISRC1_PB4.
0xCE
Read
[7:0]
0
ISRC1_PB5
ISRC1_PB5.
0xCF
Read
[6:0]
0
New data flags
New data flags (see Register 0x87).
0xD0
Read
[7:0]
0
ISRC1_PB6
ISRC1_PB6.
0xD1
Read
[7:0]
0
ISRC1_PB7
ISRC1_PB7.
0xD2
Read
[7:0]
0
ISRC1_PB8
ISRC1_PB8.
0xD3
Read
[7:0]
0
ISRC1_PB9
ISRC1_PB9.
0xD4
Read
[7:0]
0
ISRC1_PB10
ISRC1_PB10.
0xD5
Read
[7:0]
0
ISRC1_PB11
ISRC1_PB11.
0xD6
Read
[7:0]
0
ISRC1_PB12
ISRC1_PB12.
0xD7
Read
[6:0]
0
New data flags
New data flags (see Register 0x87).
0xD8
Read
[7:0]
0
ISRC1_PB13
ISRC1_PB13.
0xD9
Read
[7:0]
0
ISRC1_PB14
ISRC1_PB14.
0xDA
Read
[7:0]
0
ISRC1_PB15
ISRC1_PB15.
0xDB
Read
[7:0]
0
ISRC1_PB16
ISRC1_PB16.
0xDC
Read
[7:0]
0
ISRC2 Packet Byte 0
ISRC2 Packet Byte 0 (ISRC2_PB0). This is transmitted only
when the ISRC bit continues (Register 0xC8, Bit[7]) is set to 1.
0xDD
Read
[7:0]
0
ISRC2_PB1
ISRC2_PB1.
0xDE
Read
[7:0]
0
ISRC2_PB2
ISRC2_PB2.
0xDF
Read
[6:0]
0
New data flags
New data flags (see Register 0x87).
0xE0
Read
[7:0]
0
ISRC2_PB3
ISRC2_PB3.
0xE1
Read
[7:0]
0
ISRC2_PB4
ISRC2_PB4.
0xE2
Read
[7:0]
0
ISRC2_PB5
ISRC2_PB5.
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