參數(shù)資料
型號: AD9287-100EBZ
廠商: Analog Devices Inc
文件頁數(shù): 17/52頁
文件大?。?/td> 0K
描述: BOARD EVALUATION AD9287
設(shè)計資源: AD9219/28/59/87 Gerber Files
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 4
位數(shù): 8
采樣率(每秒): 100M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 530mW @ 100MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9287
已供物品: 板,電源
產(chǎn)品目錄頁面: 780 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9287BCPZRL7-100DKR-ND - IC ADC 8BIT QUAD 100MSPS 48LFCSP
AD9287BCPZRL7-100CT-ND - IC ADC 8BIT QUAD 100MSPS 48LFCSP
AD9287
Data Sheet
Rev. E | Page 24 of 52
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
500
–500
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 10000/15600
05966-
043
100
50
0
–100ps
0ps
100ps
Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Far Termination Only
200
–200
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 9600/15600
05966-
044
100
50
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Far Termination Only
200
400
–200
–400
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 9599/15599
05966-
042
100
50
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Far Termination Only
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D7 ... D0)
255
+1.00
1111 1111
128
0.00
1000 0000
127
0.007813
0111 1111
0
1.00
0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 8 bits
times the sample clock rate, with a maximum of 800 Mbps
(8 bits × 100 MSPS = 800 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.
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