參數資料
| 型號： | AD9279BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 30/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 80MSPS 144CSPBGA |
| 標準包裝： | 1 |
| 類型： | AAF，ADC，解調器，LNA，VGA |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 80M |
| 數據接口： | 串行，SPI? |
| 電壓電源： | 模擬和數字 |
| 電源電壓： | 1.7 V ~ 1.9 V，2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA，CSPBGA |
| 供應商設備封裝： | 144-CSPBGA（10x10） |
| 包裝： | 托盤 |
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AD9279
Rev. 0 | Page 36 of 44
the output of the AD9279 are summed in an I-to-V converter to
provide the combined output signal with a theoretical improve-
ment in dynamic range of 6 dB for the four channels.
CW Application Information
The RESET pin is used to synchronize the LO dividers in AD9279
arrays. Because they are driven by the same internal LO, the four
channels in any AD9279 are inherently synchronous. However,
when multiple AD9279s are used, it is possible that their dividers
wake up in different phase states. The function of the RESET
pin is to phase align all the LO signals in multiple AD9279s.
The 4LO divider of each AD9279 can be initiated in one of four
possible states: 0°, 90°, 180°, and 270° relative to other AD9279s.
The internally generated I/Q signals of each AD9279 LO are always
at a 90° angle relative to each other, but a phase shift can occur
during power-up between the dividers of multiple AD9279s
used in a common array.
The RESET mechanism also allows the measurement of non-
mixing gain from the RF input to the output. The rising edge of
the active high RESET pulse can occur at any time; however, the
duration should be ≥ 20 ns minimum. When the RESET pulse
transitions from high to low, the LO dividers are reactivated on
the next rising edge of the 4LO clock. To guarantee synchronous
operation of an array of AD9279s, the RESET pulse must go low
on all devices before the next rising edge of the 4LO clock.
Therefore, it is best to have the RESET pulse go low on the falling
edge of the 4LO clock; at the very least, the tSETUP should be ≥ 5 ns.
An optimal timing setup is for the RESET pulse to go high on a
4LO falling edge and to go low on a 4LO falling edge; this gives
15 ns of setup time even at a 4LO frequency of 32 MHz (8 MHz
internal LO). Use the following procedure to check the synch-
ronization of multiple AD9279s:
1.
Activate at least one channel per AD9279 by setting the
appropriate channel enable bit in the serial interface.
2.
Set the phase code of all AD9279 channels to the same
logic state, for example, 0000.
3.
Apply the same test signal to all devices to generate a sine
wave in the baseband output and measure the output of
one channel per device.
4.
Apply a RESET pulse to all AD9279s.
5.
Because all phase codes of the AD9279s should be the
same, the combined signal of multiple devices should be N
times greater than a single channel. If the combined signal
is less than N times one channel, one or more of the LO
phases of the individual AD9279s are in error.
S1
S2
S3
S4
E1
E2
E3
E4
90°
45°
135°
0°
SUMMED
OUTPUT
S1 + S2 + S3 + S4
S1 THROUGH S4
ARE NOW
IN PHASE
PHASE BIT
SETTINGS
CHANNEL 1
PHASE SET
FOR 135°
LAG
CHANNEL 2
PHASE SET
FOR 90°
LAG
CHANNEL 3
PHASE SET
FOR 45°
LAG
CHANNEL 4
PHASE SET
FOR 0°
LAG
TRANSDUCER ELEMENT TE1
THROUGH ELEMENT TE4
CONVERT US WAVES TO
ELECTRICAL SIGNALS
LNA
4 US WAVES
ARE DELAYED
45° EACH WITH
RESPECT TO
EACH OTHER
09
42
3-
0
46
Figure 67. Simplified Example of the AD9279 Phase Shifter
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