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參數(shù)資料
| 型號： | AD9262BCPZRL7-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 5MHZ 64LFCSP |
| 設計資源： | Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062) |
| 標準包裝： | 750 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 160M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 703mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，單極 |
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AD9262
Rev. A | Page 7 of 32
SWITCHING SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = 2.0 dBFS
unless otherwise noted.
Table 5.
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK INPUT (USING CLOCK MULTIPLIER)
Conversion Rate
Full
30
160
MSPS
CLK± Period
Full
6.25
33
ns
CLK± Duty Cycle
Full
40
50
60
%
CLOCK INPUT (DIRECT CLOCKING)
Conversion Rate
Full
608
640
672
MSPS
CLK± Period
Full
1.49
1.5625
1.64
ns
CLK± Duty Cycle
Full
40
50
60
%
DATA OUTPUT PARAMETERS
Output Data Rate
Full
20
160
MSPS
DCO to Data Skew (tSKEW)2
Full
3
ns
Sample Latency3
Full
960
Cycles4
WAKE-UP TIME5
Power-Down Power
Full
3
μs
Standby Power
Full
9
μs
Sleep Power
Full
15
μs
OUT-OF-RANGE RECOVERY TIME3
Full
960
Cycles4
SERIAL PORT INTERFACE6
SCLK Period
Full
40
ns
SCLK Pulse Width High Time (tSHIGH)
Full
16
ns
SCLK Pulse Width Low Time (tSLOW)
Full
16
ns
SDIO to SCLK Setup Time (tSDS)
Full
5
ns
SDIO to SCLK Hold Time (tSDH)
Full
2
ns
CSB to SCLK Setup Time (tSS)
Full
5
ns
CSB to SCLK Hold Time (tSH)
Full
2
ns
1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Data skew is measured from DCO 50% transition to data (D0x to D15x) 50% transition, with 5 pF load.
3 Typical measured value for the AD9262BCPZ-10. For the AD9262BCPZ-5 and the AD9262BCPZ, typical values double and quadruple the number of cycles, respectively.
4 Cycles refers to modulator clock cycles.
5 Wake-up time is dependent on the value of the decoupling capacitor, value shown with 10uF capacitor on VREF and CFILT.
6 See Figure 60 and the Serial Port Interface (SPI) section.
Timing Diagram
07
77
2
-00
2
DCO
D0x TO D15x
tSKEW
Figure 2. Timing Diagram
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相關代理商/技術參數(shù) |
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| AD9262-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9262BCPZ 制造商:Analog Devices 功能描述:16 BIT DUAL BANDWIDTH ADC EB - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:A/D Converter Eval. Board 制造商:Analog Devices 功能描述:A/D Converter Eval. Board; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9262; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Software, Evaluation Board |
| AD9265 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 125 MSPS/105 MSPS/80 MSPS 1.8 V Analog-to-Digital Converter |
| AD9265-105EBZ | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 16 Bit 105 Msps high SNR 1.8 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9265-125EBZ | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 16 Bit 125 Msps high SNR 1.8 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9265-80EBZ | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 16 Bit 80 Msps high SNR 1.8 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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