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參數(shù)資料
| 型號： | AD9258BCPZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 125MSPS DL 64LFCSP |
| 設(shè)計資源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 788mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個差分，單極 |
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AD9258
Rev. A | Page 32 of 44
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 81, the power dissipated by the AD9258
varies with its sample rate. In CMOS output mode, the digital
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (28 plus two DCO
outputs, in the case of the AD9258).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers
reduces digital power consumption. The data in Figure 81 was
taken in LVDS output mode, using the same operating conditions
as those used for the Typical Performance Characteristics section.
1.25
1.00
0.75
0.50
0.25
0.5
0.4
0.3
0.2
0.1
0
25
50
IAVDD
IDRVDD
75
100
125
ENCODE FREQUENCY (MHz)
T
O
TA
L
P
O
W
E
R
(W
)
SU
PP
L
Y
C
U
R
E
N
T
(
A
)
08
12
4-
0
56
TOTAL POWER
Figure 81. AD9258-125 Power and Current vs. Encode Frequency (LVDS
Output Mode)
1.0
0.8
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0
25
35
45
55
65
75
85
95
105
ENCODE FREQUENCY (MSPS)
T
O
TA
L
P
O
W
E
R
(W
)
S
UP
P
L
Y
CURR
E
NT
(
A)
08
12
4-
08
6
TOTAL POWER
IAVDD
IDRVDD
Figure 82. AD9258-105 Power and Current vs. Encode Frequency (LVDS
Output Mode)
1.0
0.8
0.6
0.4
0.2
0
0.25
0.20
0.15
0.10
0.05
0
25
35
45
55
65
75
ENCODE FREQUENCY (MSPS)
TO
T
A
L
P
O
WE
R
(W
)
S
UP
P
L
Y
CURR
E
NT
(
A)
08
12
4-
08
7
TOTAL POWER
IAVDD
IDRVDD
Figure 83. AD9258-80 Power and Current vs. Encode Frequency (LVDS
Output Mode)
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9258 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9258 to its normal operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required.
DIGITAL OUTPUTS
The AD9258 output drivers can be configured to interface with
1.8 V CMOS logic families. The AD9258 can also be configured
for LVDS outputs (standard ANSI or reduced output swing mode),
using a DRVDD supply voltage of 1.8 V.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The default output mode is CMOS, with each channel output
on separate busses as shown in Figure 2. The output can also be
configured for interleaved CMOS via the SPI port. In interleaved
CMOS mode, the data for both channels is output through the
Channel A output bits, and the Channel B output is placed into
high impedance mode. The timing diagram for interleaved CMOS
output mode is shown in Figure 3.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9258BCPZ-1251 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| AD9258BCPZ-80 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14 bit 80 high SNR ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9258BCPZ-801 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| AD9258BCPZRL7-105 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14 bit 105 highSNR ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9258BCPZRL7-1051 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
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