參數(shù)資料
型號： AD9258BCPZ-125
廠商： Analog Devices Inc
文件頁數(shù)： 24/44頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 125MSPS DL 64LFCSP
設(shè)計資源： High Performance, Dual Channel IF Sampling Receiver (CN0140)
標準包裝： 1
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 788mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 2 個差分，單極
AD9258
Rev. A | Page 30 of 44
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 62). The internal buffer generates the positive
and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
0.5
1.0
1.5
2.0
0
–0.5
–1.0
–1.5
–2.0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
RE
F
E
RE
NCE
V
O
L
T
A
G
E
RRO
R
(
m
V
)
08
12
4-
0
55
VREF = 1.0V
Figure 73. Typical VREF Drift
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9258 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
(see Figure 74) and require no external bias. If the inputs are
floated, the CLK pin is pulled low to prevent spurious clocking.
0
81
24
-04
4
AVDD
CLK+
4pF
CLK–
0.9V
Figure 74. Equivalent Clock Input Circuit
Clock Input Options
The AD9258 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9258 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9258 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9258 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9258
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
08
12
4-
0
4
5
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
0
812
4-
0
46
ADC
AD9258
Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The AD9510/AD9511/AD9512/
drivers offer excellent jitter performance.
100
0.1F
240
240
PECL DRIVER
50k
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD951x
0
812
4-
047
ADC
AD9258
Figure 77. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9518 clock drivers offer excellent jitter performance.
100
0.1F
50k
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
0
812
4-
048
ADC
AD9258
Figure 78. Differential LVDS Sample Clock (Up to 625 MHz)
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