- 您現(xiàn)在的位置：買賣IC網 > PDF目錄10511 > AD9253BCPZ-105 (Analog Devices Inc)IC ADC 14BIT SRL 105MSPS 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9253BCPZ-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 105MSPS 48LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 功率耗散（最大）： | 481mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
AD9253
Data Sheet
Rev. 0 | Page 26 of 40
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 log10
J
A
t
f
2
1
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9253.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
N
R
(
d
B)
10065
-070
Figure 68. Ideal SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 69, the power dissipated by the AD9253 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
350
300
250
200
150
100
10
130
A
NA
L
O
G
CO
RE
P
O
W
E
R
(
m
W
)
SAMPLE RATE (MSPS)
10
065-
07
1
20
30
40
50
60
70
80
90
100 110
120
50 MSPS
80 MSPS
125 MSPS
40 MSPS
20 MSPS
65 MSPS
105 MSPS
Figure 69. Analog Core Power vs. fSAMPLE for fIN = 10.3 MHz
The AD9253 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the AD9253 to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When
using the SPI port interface, the user can place the ADC in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details on using these features.
相關PDF資料 |
PDF描述 |
|---|---|
| EXP-0911/05/S | CONN PLUG 5POS IP68 W/SOCKETS |
| LTC2172CUKG-14#PBF | IC ADC 14BIT SER/PAR 65M 52-QFN |
| LTC2268IUJ-14#PBF | IC ADC 14BIT SER 125MSPS 40-QFN |
| AD9633BCPZ-125 | IC ADC 12BIT SRL 125MSPS 48LFCSP |
| PT06A-16-8S | CONN PLUG 8 POS STRAIGHT W/SCKT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9253BCPZ-125 | 功能描述:IC ADC 14BIT SRL 125MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9253BCPZ-80 | 功能描述:IC ADC 14BIT SRL 80MSPS 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9253BCPZRL7-105 | 功能描述:模數(shù)轉換器 - ADC 14 Bit 105Msps Quad ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9253BCPZRL7-125 | 功能描述:模數(shù)轉換器 - ADC 14 Bit 125Msps Quad ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9253BCPZRL7-80 | 功能描述:模數(shù)轉換器 - ADC 14 Bit 80 Msps Quad ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
發(fā)布緊急采購，3分鐘左右您將得到回復。