參數(shù)資料
型號： AD9253BCPZ-105
廠商： Analog Devices Inc
文件頁數(shù)： 16/40頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 105MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 481mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 4 個差分，雙極
Data Sheet
AD9253
Rev. 0 | Page 23 of 40
Differential Input Configurations
There are several ways to drive the AD9253 either actively or
passively. However, optimum performance is achieved by driving
the analog inputs differentially. Using a differential double balun
configuration to drive the AD9253 provides excellent performance
and a flexible interface to the ADC (see Figure 58) for baseband
applications.
For applications where SNR is a key parameter, differential trans-
former coupling is the recommended input configuration (see
Figure 59), because the noise performance of most amplifiers is
not adequate to achieve the true performance of the AD9253.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
It is not recommended to drive the AD9253 inputs single-ended.
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9253. VREF can be configured using either the internal 1.0 V
reference or an externally applied 1.0 V reference voltage. The
various reference modes are summarized in the Internal Reference
section. The VREF pin should be externally decoupled to
ground with a low ESR, 1.0 μF capacitor in parallel with a low
ESR, 0.1 μF ceramic capacitor.
Internal Reference Connection
A comparator within the AD9253 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 57), setting VREF to 1.0 V.
Table 9. Reference Configuration Summary
Selected Mode
SENSE
Voltage (V)
Resulting
VREF (V)
Resulting
Differential
Span (V p-p)
Fixed Internal
Reference
AGND to
0.2
1.0 internal
2.0
Fixed External
Reference
AVDD
1.0 applied
to external
VREF pin
2.0
VREF
SENSE
0.5V
ADC
SELECT
LOGIC
0.1F
1.0F
VIN–A/VIN–B
VIN+A/VIN+B
ADC
CORE
10
06
5-
06
0
Figure 57. Internal Reference Configuration
ADC
R
0.1F
2V p-p
VCM
C
*C1
C
R
0.1F
33
200
33
VIN+x
VIN–x
100
65-
059
ET1-1-I3
C
5pF
R
*C1 IS OPTIONAL
Figure 58. Differential Double Balun Input Configuration for Baseband Applications
2V p-p
R
*C1
*C1 IS OPTIONAL
49.9
0.1μF
ADT1-1WT
1:1 Z RATIO
VIN–x
ADC
VIN+x
*C1
C
VCM
10
065-
05
6
33
200
0.1F
5pF
Figure 59. Differential Transformer-Coupled Configuration
for Baseband Applications
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