參數(shù)資料
型號(hào)： AD9253BCPZ-105
廠商： Analog Devices Inc
文件頁數(shù)： 17/40頁
文件大小： 0K
描述： IC ADC 14BIT SRL 105MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 481mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-WQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 4 個(gè)差分，雙極
AD9253
Data Sheet
Rev. 0 | Page 24 of 40
3.0
If the internal reference of the AD9253 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 60 shows
how the internal reference voltage is affected by loading.
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
0
2.5
2.0
1.5
1.0
0.5
V
RE
F
E
R
RO
R
(
%
)
LOAD CURRENT (mA)
1006
5-
061
INTERNAL VREF = 1V
Figure 60. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 61 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
–8
–40
85
V
RE
F
E
RRO
R
(
m
V
)
TEMPERATURE (°C)
10
065
-06
2
–6
–4
–2
0
2
–15
10
35
60
Figure 61. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 54). The internal buffer generates the
positive and negative full-scale references for the ADC core. There-
fore, the external reference must be limited to a maximum of 1.0 V.
It is not recommended to leave the SENSE pin floating.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9253 sample clock
inputs, CLK+ and CLK, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK pins via a
transformer or capacitors. These pins are biased internally
(see Figure 48) and require no external bias.
Clock Input Options
The AD9253 has a flexible clock input structure. The clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
Figure 62 and Figure 63 show two preferred methods for clock-
ing the AD9253 (at clock rates up to 1 GHz prior to internal CLK
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9253 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9253 while
preserving the fast rise and fall times of the signal that are critical
to achieving low jitter performance. However, the diode
capacitance comes into play at frequencies above 500 MHz. Care
must be taken in choosing the appropriate signal limiting diode.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
1
006
5-
06
4
Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
CLOCK
INPUT
0.1F
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
1
006
5-
065
Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 65. The AD9510/AD9511/AD9512/
excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 66. The AD9510/
clock drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
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