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參數(shù)資料
| 型號： | AD9216BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT DUAL 80MSPS 64LFCSP |
| 標準包裝： | 750 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 255mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
| 配用： | AD9216-80PCBZ-ND - BOARD EVAL FOR AD9216 80MSPS AD9216-105PCBZ-ND - BOARD EVAL FOR AD9216 105MSPS |
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AD9216
Rev. A | Page 11 of 40
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Pulse-width high is the minimum amount of time that the
clock pulse should be left in a Logic 1 state to achieve rated
performance; pulse-width low is the minimum time clock pulse
should be left in a low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Crosstalk
Coupling onto one channel being driven by a low level (40
dBFS) signal when the adjacent interfering channel is driven by
a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input
Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and by taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
The ENOB is calculated from the measured SINAD based on
the equation (assuming full-scale input)
6.02
dB
1.76
=
MEASURED
SINAD
ENOB
Full-Scale Input Power
Expressed in dBm and computed using the following equation.
=
0.001
V
log
10
2
INPUT
SCALE
FULL
SCALE
FULL
Z
rms
Power
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaran-
teed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a 50% crossing of the CLK rising edge and
the time when all output data bits are within valid logic levels.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9218 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| AD9218_06 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-to-Digital Converter |
| AD9218-105PCB | 制造商:Analog Devices 功能描述:DUAL 10 BIT 105/80/65 MSPS ADC EVAL BD. - Bulk |
| AD9218-65PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| AD9218BST-105 | 功能描述:IC ADC 10BIT DUAL 105MSPS 48LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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