參數(shù)資料
型號： AD9216BCPZRL7-80
廠商： Analog Devices Inc
文件頁數(shù)： 18/40頁
文件大小： 0K
描述： IC ADC 10BIT DUAL 80MSPS 64LFCSP
標準包裝： 750
位數(shù)： 10
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 2
功率耗散（最大）： 255mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
配用： AD9216-80PCBZ-ND - BOARD EVAL FOR AD9216 80MSPS
AD9216-105PCBZ-ND - BOARD EVAL FOR AD9216 105MSPS
AD9216
Rev. A | Page 25 of 40
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 49 shows the typical drift
characteristics of the internal reference.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V. If the internal reference of the AD9216 is
used to drive multiple converters to improve gain matching,
the loading of the reference by the other converters must be
considered. Figure 50 depicts how the internal reference
voltage is affected by loading.
VIN+
VIN–
VREF
REFT
SENSE
0.5V
AD9216
REFB
R1
R2
10
F
10
F
0.1
F
0.1
F
10
F
ADC
CORE
SELECT
LOGIC
0.1
F
04775-
015
Figure 48. Programmable Reference Configuration (one channel shown)
04775-016
TEMPERATURE (
°C)
VR
EF
ER
R
O
R
(
%
) 0.4
0.5
0.6
0.3
0.2
0.1
0
–40
–20
0
2040
6080
VREF = 1.0V
Figure 49. Typical VREF Drift
04775-017
ILOAD (mA)
VR
EF
ER
R
O
R
(
%
)
0
0.05
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
VREF = 1.0V
Figure 50. VREF Accuracy vs. Load
Shared Reference Mode
The shared reference mode allows the user to connect
the references from the dual ADCs together externally for
superior gain and offset matching performance. If the ADCs
are to function independently, the reference decoupling can
be treated independently and can provide superior isolation
between the dual channels. To enable shared reference mode,
the SHARED_REF pin must be tied high, and the external
differential references must be externally shorted. (REFT_A
must be externally shorted to REFT_B, and REFB_A must
be shorted to REFB_B.)
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