
AD9211
Rev. 0 | Page 24 of 28
Table 11. Serial Timing Definitions
Parameter
Timing (minimum, ns)
Description
tDS
5
Setup time between the data and the rising edge of SCLK
tDH
2
Hold time between the data and the rising edge of SCLK
tCLK
40
Period of the clock
tS
5
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHI
16
Minimum period that SCLK should be in a logic high state
tLO
16
Minimum period that SCLK should be in a logic low state
tEN_SDIO
1
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
tDIS_SDIO
5
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
Table 12. Output Data Format
Input (V)
Condition (V)
Offset Binary
Output Mode
D11 to D0
Twos Complement Mode
D11 to D0
Gray Code Mode
(SPI Accessible)
D11 to D0
OR
VIN+ VIN
< 0.62
0000 0000 00
1
VIN+ VIN
= 0.62
0000 0000 00
0
VIN+ VIN
= 0
0000 0000 00
0
VIN+ VIN
= 0.62
1111 1111 11
0000 0000 00
0
VIN+ VIN
> 0.62 + 0.5 LSB
1111 1111 11
0000 0000 00
1