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參數(shù)資料
| 型號(hào)： | AD8600CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Channel, 8-Bit Multiplying DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, UUC43 |
| 封裝： | DIE |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 236K |
| 代理商： | AD8600CHIPS |
REV. 0
–4–
AD8600
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
T yp
Max
Units
INT ERFACE T IMING
1, 2
Clock (
EN
) Frequency
Clock (
EN
) High Pulse Width
Clock (
EN
) LowPulse Width
Data Setup T ime
Data Hold T ime
Address Setup T ime
Address Hold T ime
Valid Address to Data Valid
Load Enable Setup T ime
Load Enable Hold T ime
Read/Write to Clock (
EN
)
Read/Write to DataBus Hi-Z
Read/Write to DataBus Active
Clock (
EN
) to Read/Write
Clock (
EN
) to Chip Select
Chip Select to Clock (
EN
)
Chip Select to Data Valid
Chip Select to DataBus Hi-Z
Reset Pulse Width
f
CLK
t
CH
t
CL
t
DS
t
DH
t
AS
t
AH
t
AD
t
LS
t
LH
t
RWC
t
RWZ
t
RWD
t
T WH
t
T CH
t
CSC
t
CSD
t
CSZ
t
RS
Data Loading
12.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
40
40
10
0
0
160
0
0
30
120
120
0
0
30
120
150
25
NOT ES
1
Guaranteed by design not subject to production test.
2
All logic input signals have maximum rise and fall times of 2 ns.
Specifications subject to change without notice.
Figure 3. Readback Timing
Figure 2. Write Timing
(@ V
DD1
= V
DD2
= V
CC
= +5V
±
5%, V
EE
= –5V, V
REF
= +3.500V, –40
°
C
≤
T
A
≤
+85
°
C,
unless otherwse noted)
t
RWZ
t
DH
t
TWH
HIGH-Z
t
AS
t
AH
t
CH
t
CL
t
TCH
R/
W
DATA
ADDR
EN
CS
t
CSC
t
RWC
t
DS
Figure 4. Write to DAC Register & Voltage Output Settling
Timing (CS= High, Prevents Input Register Changes)
t
LS
t
LH
t
S1
t
RS
OUT
t
S1
EN
RS
LD
t
RWD
HIGH -Z
t
AD
t
CSZ
t
CSD
R/
W
DATA
ADDR
EN
CS
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